; RUN: llc < %s -O0 -march=x86 | FileCheck %s

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@glbl = extern_weak constant i8

declare i64 @llvm.expect.i64(i64, i64) #0

define void @test() {
; CHECK: movl $glbl
  %tmp = call i64 @llvm.expect.i64(i64 zext (i1 icmp eq (i8* @glbl, i8* null) to i64), i64 0)
  %tmp2 = icmp ne i64 %tmp, 0
  br i1 %tmp2, label %bb1, label %bb2

bb1:
  unreachable

bb2:
  unreachable
}

attributes #0 = { nounwind readnone }

Remove unnecessary attributes from test case.

; RUN: llc < %s -O0 -march=x86 | FileCheck %s

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@glbl = extern_weak constant i8

declare i64 @llvm.expect.i64(i64, i64)

define void @test() {
; CHECK: movl $glbl
  %tmp = call i64 @llvm.expect.i64(i64 zext (i1 icmp eq (i8* @glbl, i8* null) to i64), i64 0)
  %tmp2 = icmp ne i64 %tmp, 0
  br i1 %tmp2, label %bb1, label %bb2

bb1:
  unreachable

bb2:
  unreachable
}


; Test that pure functions are cse'd away

; RUN: llvm-as < %s | opt -globalsmodref-aa -load-vn -gcse -instcombine -adce| llvm-dis | not grep call

int %pure(int %X) {
	%Y = add int %X, 1
	ret int %Y
}

int %test(int %X) {
	%A = call int %pure(int %X)
	%B = call int %pure(int %X)
	%C = sub int %A, %B
	ret int %C
}

Change the test to check to see that CSE happens not dead call elim

; Test that pure functions are cse'd away

; RUN: llvm-as < %s | opt -globalsmodref-aa -load-vn -gcse -instcombine | llvm-dis | not grep sub

int %pure(int %X) {
	%Y = add int %X, 1
	ret int %Y
}

int %test(int %X) {
	%A = call int %pure(int %X)
	%B = call int %pure(int %X)
	%C = sub int %A, %B
	ret int %C
}


; RUN: opt < %s -argpromotion -S | FileCheck %s
; CHECK: call void @test(), !dbg !1
target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
define internal void @test(i32* %X) {
  ret void
}

define void @caller() {
  call void @test(i32* null), !dbg !1
  ret void
}

!llvm.module.flags = !{!3}

!1 = metadata !{i32 8, i32 0, metadata !2, null}
!2 = metadata !{}
!3 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}

Remove unnecessary datalayout string from a test case.

; RUN: opt < %s -argpromotion -S | FileCheck %s
; CHECK: call void @test(), !dbg !1

define internal void @test(i32* %X) {
  ret void
}

define void @caller() {
  call void @test(i32* null), !dbg !1
  ret void
}

!llvm.module.flags = !{!3}

!1 = metadata !{i32 8, i32 0, metadata !2, null}
!2 = metadata !{}
!3 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}


; RUN: llvm-upgrade < %s | llvm-as -o /dev/null -f

; This should parse correctly without an 'implementation', but our current YACC
; based parser doesn't have the required 2 token lookahead...

%T = type int *

%T %test() {
	ret %T null
}

Make this test that we can drop the implementation keyword for llvm-as. llvm-upgrade is irrelevant for this test case.

; RUN: llvm-as %s -o /dev/null -f

; This should parse correctly without an 'implementation', but our current YACC
; based parser doesn't have the required 2 token lookahead...

%T = type i32 *

define %T %test() {
	ret %T null
}


; Make sure that for each supported architecture in RelocVisitor::visit,
; the visitor does compute the relocation. This should test all archs that
; have buildbots. We can't set all archs, since some bots don't build all
; back-ends.
; RUN: llc -filetype=obj -O0 < %s | llvm-dwarfdump - 2>&1 | FileCheck %s
; XFAIL: i686, i386, hexagon

; CHECK-NOT: failed to compute relocation

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!llvm.ident = !{!5}

!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.6.0 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/a/empty.c] [DW_LANG_C99]
!1 = metadata !{metadata !"empty.c", metadata !"/a"}
!2 = metadata !{}
!3 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
!4 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}
!5 = metadata !{metadata !"clang version 3.6.0 "}

Revert 218411 - XFAIL reloc test on x86/hexagon

; Make sure that for each supported architecture in RelocVisitor::visit,
; the visitor does compute the relocation. This should test all archs that
; have buildbots. We can't set all archs, since some bots don't build all
; back-ends.
; RUN: llc -filetype=obj -O0 < %s | llvm-dwarfdump - 2>&1 | FileCheck %s

; CHECK-NOT: failed to compute relocation

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!llvm.ident = !{!5}

!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.6.0 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/a/empty.c] [DW_LANG_C99]
!1 = metadata !{metadata !"empty.c", metadata !"/a"}
!2 = metadata !{}
!3 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
!4 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}
!5 = metadata !{metadata !"clang version 3.6.0 "}


(progn
  (nil: -999)
  (zero?: [x] (= x 0))
  (empty?: [l] (if (atom? l) (= l nil) 0))

  (reverse: [l]
    (let ((reverseaux [l res]
            (tif (empty? l)
                 res
                 (recur (cdr l) (cons (car l) res)))))
         (reverseaux l nil)))

  (nth: [li n]
    (tif (zero? n)
         (car li)
         (recur (cdr li) (- n 1))))

  (map: [l f]
    (let ((mapaux [l f res]
             (tif (empty? l)
                  (reverse res)
                  (recur (cdr l) f (cons (f (car l)) res)))))
         (mapaux l f nil)))

  (map (cons 1 (cons 2 (cons 3 (cons 4 nil)))) [x] (+ 2 x))
)

Add a pseudo-random number generator

(progn
  (nil: -999)
  (seed: 1)
  (zero?: [x] (= x 0))
  (empty?: [l] (if (atom? l) (= l nil) 0))

  (reverse: [l]
    (let ((reverseaux [l res]
            (tif (empty? l)
                 res
                 (recur (cdr l) (cons (car l) res)))))
         (reverseaux l nil)))

  (nth: [li n]
    (tif (zero? n)
         (car li)
         (recur (cdr li) (- n 1))))

  (map: [l f]
    (let ((mapaux [l f res]
             (tif (empty? l)
                  (reverse res)
                  (recur (cdr l) f (cons (f (car l)) res)))))
         (mapaux l f nil)))

  (expt: [v n]
     (if (= n 0)
         1
         (* v (self v (- n 1)))))

  (mod: [n m]
    (- n (* (/ n m) m)))

  (random: []
    (let ((m (- (expt 2 31) 1))
           (a 48271)
           (c 1))
      (defvar seed (mod (+ (* a seed) c) m))))

  (genrandom: [n]
    (if (= n 0)
        nil
        (cons (random) (self (- n 1)))))

  (genrandom 10))


; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | \
; RUN:   %prcontext 'mulss LCPI1_3' 1 | grep mulss | wc -l | grep 1

define float %foo(float %x) {
    %tmp1 = mul float %x, 3.000000e+00
    %tmp3 = mul float %x, 5.000000e+00
    %tmp5 = mul float %x, 7.000000e+00
    %tmp7 = mul float %x, 1.100000e+01
    %tmp10 = add float %tmp1, %tmp3
    %tmp12 = add float %tmp10, %tmp5
    %tmp14 = add float %tmp12, %tmp7
    ret float %tmp14
}

Add PR number for future reference

; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | \
; RUN:   %prcontext 'mulss LCPI1_3' 1 | grep mulss | wc -l | grep 1
; PR1075

define float %foo(float %x) {
    %tmp1 = mul float %x, 3.000000e+00
    %tmp3 = mul float %x, 5.000000e+00
    %tmp5 = mul float %x, 7.000000e+00
    %tmp7 = mul float %x, 1.100000e+01
    %tmp10 = add float %tmp1, %tmp3
    %tmp12 = add float %tmp10, %tmp5
    %tmp14 = add float %tmp12, %tmp7
    ret float %tmp14
}


; RUN: llvm-as %s -o %t.o

; RUN: not %gold -plugin %llvmshlibdir/LLVMgold.so \
; RUN:    --plugin-opt=emit-llvm \
; RUN:    -shared %t.o -o %t2.o 2>&1 | FileCheck %s

; CHECK: Unable to determine comdat of alias!

@g1 = global i32 1
@g2 = global i32 2

@a = alias inttoptr(i32 sub (i32 ptrtoint (i32, inttoptr(i32 sub (i32 ptrtoint (i32* @g1 to i32),
                             i32 ptrtoint (i32* @g2 to i32)) to i32*)

Fix the gold test cases after alias changes

; RUN: llvm-as %s -o %t.o

; RUN: not %gold -plugin %llvmshlibdir/LLVMgold.so \
; RUN:    --plugin-opt=emit-llvm \
; RUN:    -shared %t.o -o %t2.o 2>&1 | FileCheck %s

; CHECK: Unable to determine comdat of alias!

@g1 = global i32 1
@g2 = global i32 2

@a = alias i32, inttoptr(i32 sub (i32 ptrtoint (i32, inttoptr(i32 sub (i32 ptrtoint (i32* @g1 to i32),
                             i32 ptrtoint (i32* @g2 to i32)) to i32*)


; RUN: llvm-as < %s >%t.bc

; RUN: rm -f %t.yaml
; RUN: llvm-lto2 -pass-remarks-output=%t.yaml \
; RUN:           -r %t.bc,tinkywinky,p \
; RUN:           -r %t.bc,patatino,px \
; RUN:           -r %t.bc,main,px -o %t.o %t.bc 2>&1
; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML

; YAML:      --- !Passed
; YAML-NEXT: Pass:            inline
; YAML-NEXT: Name:            Inlined
; YAML-NEXT: Function:        main
; YAML-NEXT: Args:
; YAML-NEXT:   - Callee:          tinkywinky
; YAML-NEXT:   - String:          ' inlined into '
; YAML-NEXT:   - Caller:          main
; YAML-NEXT: ...

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-scei-ps4"

declare i32 @patatino()

define i32 @tinkywinky() {
  %a = call i32 @patatino()
  ret i32 %a
}

define i32 @main() {
  %i = call i32 @tinkywinky()
  ret i32 %i
}

Remove useless redirection from test. NFCI.

; RUN: llvm-as < %s >%t.bc

; RUN: rm -f %t.yaml
; RUN: llvm-lto2 -pass-remarks-output=%t.yaml \
; RUN:           -r %t.bc,tinkywinky,p \
; RUN:           -r %t.bc,patatino,px \
; RUN:           -r %t.bc,main,px -o %t.o %t.bc
; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML

; YAML:      --- !Passed
; YAML-NEXT: Pass:            inline
; YAML-NEXT: Name:            Inlined
; YAML-NEXT: Function:        main
; YAML-NEXT: Args:
; YAML-NEXT:   - Callee:          tinkywinky
; YAML-NEXT:   - String:          ' inlined into '
; YAML-NEXT:   - Caller:          main
; YAML-NEXT: ...

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-scei-ps4"

declare i32 @patatino()

define i32 @tinkywinky() {
  %a = call i32 @patatino()
  ret i32 %a
}

define i32 @main() {
  %i = call i32 @tinkywinky()
  ret i32 %i
}


; REQUIRES: shell
; RUN: llvm-link %s %S/Inputs/targettriple-a.ll -S -o - 2>%t.a.err | FileCheck %s
; RUN: (echo foo ;cat %t.a.err) | FileCheck --check-prefix=WARN-A %s

; RUN: llvm-link %s %S/Inputs/targettriple-b.ll -S -o - 2>%t.b.err | FileCheck %s
; RUN: cat %t.b.err | FileCheck --check-prefix=WARN-B %s

target triple = "e"

; CHECK: target triple = "e"

; WARN-A-NOT: WARNING

; WARN-B: WARNING: Linking two modules of different target triples:

Add a test for the -suppress-warnings option.

; REQUIRES: shell
; RUN: llvm-link %s %S/Inputs/targettriple-a.ll -S -o - 2>%t.a.err | FileCheck %s
; RUN: (echo foo ;cat %t.a.err) | FileCheck --check-prefix=WARN-A %s

; RUN: llvm-link %s %S/Inputs/targettriple-b.ll -S -o - 2>%t.b.err | FileCheck %s
; RUN: cat %t.b.err | FileCheck --check-prefix=WARN-B %s

; RUN: llvm-link -suppress-warnings %s %S/Inputs/targettriple-b.ll -S -o - 2>%t.no-warn.err | FileCheck %s
; RUN: (echo foo ;cat %t.no-warn.err) | FileCheck --check-prefix=WARN-A %s

target triple = "e"

; CHECK: target triple = "e"

; WARN-A-NOT: WARNING

; WARN-B: WARNING: Linking two modules of different target triples:


; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
; PR/4004

@i = thread_local global i32 15

define i32 @f() {
entry:
	%tmp1 = load i32* @i
	ret i32 %tmp1
}

Fix the syntax for a PR number in a test.

; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
; RUN: llvm-as < %s | llc -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
; PR4004

@i = thread_local global i32 15

define i32 @f() {
entry:
	%tmp1 = load i32* @i
	ret i32 %tmp1
}


; This test makes sure that these instructions are properly eliminated.
;

; RUN: if as < %s | opt -instcombine | dis | grep set
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

%X = uninitialized global int

bool "test1"(int %A) {
	%B = seteq int %A, %A
	%C = seteq int* %X, null   ; Never true
	%D = and bool %B, %C
	ret bool %D
}

bool "test2"(int %A) {
	%B = setne int %A, %A
	%C = setne int* %X, null   ; Never false
	%D = or bool %B, %C
	ret bool %D
}

bool "test3"(int %A) {
	%B = setlt int %A, %A
	ret bool %B
}

bool "test4"(int %A) {
	%B = setgt int %A, %A
	ret bool %B
}

bool "test5"(int %A) {
	%B = setle int %A, %A
	ret bool %B
}

bool "test6"(int %A) {
	%B = setge int %A, %A
	ret bool %B
}

Add some more features that we could instcombine away

; This test makes sure that these instructions are properly eliminated.
;

; RUN: if as < %s | opt -instcombine | dis | grep set
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

%X = uninitialized global int

bool "test1"(int %A) {
	%B = seteq int %A, %A
	%C = seteq int* %X, null   ; Never true
	%D = and bool %B, %C
	ret bool %D
}

bool "test2"(int %A) {
	%B = setne int %A, %A
	%C = setne int* %X, null   ; Never false
	%D = or bool %B, %C
	ret bool %D
}

bool "test3"(int %A) {
	%B = setlt int %A, %A
	ret bool %B
}

bool "test4"(int %A) {
	%B = setgt int %A, %A
	ret bool %B
}

bool "test5"(int %A) {
	%B = setle int %A, %A
	ret bool %B
}

bool "test6"(int %A) {
	%B = setge int %A, %A
	ret bool %B
}

bool "test7"(uint %A) {
	%B = setge uint %A, 0  ; true
	ret bool %B
}

bool "test8"(uint %A) {
	%B = setlt uint %A, 0  ; false
	ret bool %B
}


; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
; dependency) when it isn't dependent on last CPSR defining instruction.
; rdar://8928208

define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
 entry:
; CHECK: t:
; CHECK: muls r2, r2, r3
; CHECK-NEXT: mul  r0, r0, r1
; CHECK-NEXT: muls r0, r0, r2
  %0 = mul nsw i32 %a, %b
  %1 = mul nsw i32 %c, %d
  %2 = mul nsw i32 %0, %1
  ret i32 %2
}

Use regex to remove false dependencies on register allocation.

; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
; dependency) when it isn't dependent on last CPSR defining instruction.
; rdar://8928208

define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
 entry:
; CHECK: t:
; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r0, r1
; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
  %0 = mul nsw i32 %a, %b
  %1 = mul nsw i32 %c, %d
  %2 = mul nsw i32 %0, %1
  ret i32 %2
}


; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \
; RUN:   grep {mov r11, sp}
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \
; RUN:   grep {mov sp, r11}

define void @f(i32 %a) {
entry:
        %tmp = alloca i8, i32 %a                ; <i8*> [#uses=1]
        call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 )
        ret void
}

declare void @g(i8*, i32, i32, i32, i32)

Convert to FileCheck, fixing failure due to tab change in the process.

; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s

define void @f(i32 %a) {
entry:
; CHECK: mov r11, sp
        %tmp = alloca i8, i32 %a                ; <i8*> [#uses=1]
        call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 )
        ret void
; CHECK: mov sp, r11
}

declare void @g(i8*, i32, i32, i32, i32)


; RUN: llvm-as < %s | llc -march=x86 > %t
; grep {movzbl	%\[abcd\]h,} %t | count 1
; grep {shll	\$3,} | count 1

; Use an h register, but don't omit the explicit shift for
; non-address use(s).

define i32 @foo(i8* %x, i32 %y) nounwind {
	%t0 = lshr i32 %y, 8		; <i32> [#uses=1]
	%t1 = and i32 %t0, 255		; <i32> [#uses=2]
        %t2 = shl i32 %t1, 3
	%t3 = getelementptr i8* %x, i32 %t2		; <i8*> [#uses=1]
	store i8 77, i8* %t3, align 4
	ret i32 %t2
}

Fix the RUN lines so that this test actually tests.

; RUN: llvm-as < %s | llc -march=x86 > %t
; RUN: grep {movzbl	%\[abcd\]h,} %t | count 1
; RUN: grep {shll	\$3,} %t | count 1

; Use an h register, but don't omit the explicit shift for
; non-address use(s).

define i32 @foo(i8* %x, i32 %y) nounwind {
	%t0 = lshr i32 %y, 8		; <i32> [#uses=1]
	%t1 = and i32 %t0, 255		; <i32> [#uses=2]
        %t2 = shl i32 %t1, 3
	%t3 = getelementptr i8* %x, i32 %t2		; <i8*> [#uses=1]
	store i8 77, i8* %t3, align 4
	ret i32 %t2
}


; RUN: llc < %s | FileCheck --check-prefix=CTOR %s
; RUN: llc -use-init-array < %s | FileCheck --check-prefix=INIT-ARRAY %s
@llvm.global_ctors = appending global [2 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @f }, { i32, void ()* } { i32 15, void ()* @g }]

define void @f() {
entry:
  ret void
}

define void @g() {
entry:
  ret void
}

; CTOR:		.section	.ctors.65520,"aw",@progbits
; CTOR-NEXT:	.align	8
; CTOR-NEXT:	.quad	g
; CTOR-NEXT:	.section	.ctors,"aw",@progbits
; CTOR-NEXT:	.align	8
; CTOR-NEXT:	.quad	f

; INIT-ARRAY:		.section	.init_array.15,"aw",@init_array
; INIT-ARRAY-NEXT:	.align	8
; INIT-ARRAY-NEXT:	.quad	g
; INIT-ARRAY-NEXT:	.section	.init_array,"aw",@init_array
; INIT-ARRAY-NEXT:	.align	8
; INIT-ARRAY-NEXT:	.quad	f

Add a triple to the test.

; RUN: llc < %s | FileCheck --check-prefix=CTOR %s
; RUN: llc -mtriple x86_64-pc-linux -use-init-array < %s | FileCheck --check-prefix=INIT-ARRAY %s
@llvm.global_ctors = appending global [2 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @f }, { i32, void ()* } { i32 15, void ()* @g }]

define void @f() {
entry:
  ret void
}

define void @g() {
entry:
  ret void
}

; CTOR:		.section	.ctors.65520,"aw",@progbits
; CTOR-NEXT:	.align	8
; CTOR-NEXT:	.quad	g
; CTOR-NEXT:	.section	.ctors,"aw",@progbits
; CTOR-NEXT:	.align	8
; CTOR-NEXT:	.quad	f

; INIT-ARRAY:		.section	.init_array.15,"aw",@init_array
; INIT-ARRAY-NEXT:	.align	8
; INIT-ARRAY-NEXT:	.quad	g
; INIT-ARRAY-NEXT:	.section	.init_array,"aw",@init_array
; INIT-ARRAY-NEXT:	.align	8
; INIT-ARRAY-NEXT:	.quad	f


; This fails because the linker renames the non-opaque type not the opaque
; one...

; RUN: echo "%Ty = type opaque" | llvm-as > %t.1.bc
; RUN: llvm-as < %s > %t.2.bc
; RUN: llvm-link %t.[12].bc | llvm-dis | grep '%Ty ' | grep -v opaque

%Ty = type int

Correct test. use "not grep" instead of "grep -v"

; This fails because the linker renames the non-opaque type not the opaque
; one...

; RUN: echo "%Ty = type opaque %GV = external global %Ty*" | llvm-as > %t.1.bc
; RUN: llvm-as < %s > %t.2.bc
; RUN: llvm-link %t.[12].bc | llvm-dis | grep '%Ty ' | not grep opaque

%Ty = type int


; RUN: llc --march=cellspu < %s | FileCheck %s

define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
  ; CHECK: cwd {{\$.}}, 0($sp)
  ; CHECK: shufb {{\$., \$4, \$3, \$.}}
  %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3>
  ret <4 x float> %val
}

define <4 x float> @splat(float %param1) {
  %vec = insertelement <1 x float> undef, float %param1, i32 0
  %val= shufflevector <1 x float> %vec, <1 x float> undef, <4 x i32> <i32 0,i32 0,i32 0,i32 0>
  ret <4 x float> %val
}

Add the check to the testcase of r106419.

; RUN: llc --march=cellspu < %s | FileCheck %s

define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
  ; CHECK: cwd {{\$.}}, 0($sp)
  ; CHECK: shufb {{\$., \$4, \$3, \$.}}
  %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> <i32 4,i32 1,i32 2,i32 3>
  ret <4 x float> %val
}

define <4 x float> @splat(float %param1) {
  ; CHECK: lqa
  ; CHECK: shufb $3
  ; CHECK: bi
  %vec = insertelement <1 x float> undef, float %param1, i32 0
  %val= shufflevector <1 x float> %vec, <1 x float> undef, <4 x i32> <i32 0,i32 0,i32 0,i32 0>
  ret <4 x float> %val
}


; RUN: llvm-as < %s | llc -march=x86 | not grep and

; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.

; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node.

define i64 @h(i64 %d) nounwind  {
        %e = add i64 %d, 1
        %retval = and i64 %e, 281474976710655
        ret i64 %retval
}

Add an extra example that shouldn't get an and instruction.

; RUN: llvm-as < %s | llc -march=x86 | not grep and

; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions.

; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node.

define i64 @l(i64 %d) nounwind  {
        %e = add i64 %d, 1
        %retval = and i64 %e, 1099511627775
        ret i64 %retval
}
define i64 @m(i64 %d) nounwind  {
        %e = add i64 %d, 1
        %retval = and i64 %e, 281474976710655
        ret i64 %retval
}


; REQUIRES: asserts

; RUN: llvm-as < %s > %t1.bc

; Try to save statistics to file.
; RUN: llvm-lto2 run %t1.bc -o %t.o -r %t1.bc,patatino,px -stats-file=%t2.stats
; RUN: FileCheck --input-file=%t2.stats %s

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define void @patatino() {
  fence seq_cst
  ret void
}

; CHECK: {
; CHECK: "asm-printer.EmittedInsts":
; CHECK: }

; Try to save statistics to an invalid file.
; RUN: not llvm-lto2 run %t1.bc -o %t.o -r %t1.bc,patatino,px \
; RUN:     -stats-file=%t2/foo.stats 2>&1 | FileCheck --check-prefix=ERROR %s
; ERROR: LTO::run failed: No such file or directory

Fix test by allowing it to accept an upper or lower case letter as the first character.

; REQUIRES: asserts

; RUN: llvm-as < %s > %t1.bc

; Try to save statistics to file.
; RUN: llvm-lto2 run %t1.bc -o %t.o -r %t1.bc,patatino,px -stats-file=%t2.stats
; RUN: FileCheck --input-file=%t2.stats %s

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define void @patatino() {
  fence seq_cst
  ret void
}

; CHECK: {
; CHECK: "asm-printer.EmittedInsts":
; CHECK: }

; Try to save statistics to an invalid file.
; RUN: not llvm-lto2 run %t1.bc -o %t.o -r %t1.bc,patatino,px \
; RUN:     -stats-file=%t2/foo.stats 2>&1 | FileCheck --check-prefix=ERROR %s
; ERROR: LTO::run failed: {{[Nn]}}o such file or directory


; RUN: llvm-as < %s | opt -scalar-evolution -analyze | grep {Loop header: ( 0 smax  %n) iterations!}
; XFAIL: *

define void @foo(i32 %n) {
entry:
	br label %header
header:
	%i = phi i32 [ 0, %entry ], [ %i.inc, %next ]
	%cond = icmp sgt i32 %n, %i
	br i1 %cond, label %next, label %return
next:
        %i.inc = add i32 %i, 1
	br label %header
return:
	ret void
}

Fix spacing in the grep line for this test, following the recent SCEV-whitespace changes.

; RUN: llvm-as < %s | opt -scalar-evolution -analyze | grep {Loop header: (0 smax %n) iterations!}
; XFAIL: *

define void @foo(i32 %n) {
entry:
	br label %header
header:
	%i = phi i32 [ 0, %entry ], [ %i.inc, %next ]
	%cond = icmp sgt i32 %n, %i
	br i1 %cond, label %next, label %return
next:
        %i.inc = add i32 %i, 1
	br label %header
return:
	ret void
}


; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.

; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s

define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
entry:
  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
  ret i32 %0
}

declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind

; CHECK: llvm_mips_lsa_test:
; CHECK: lsa {{\$[0-9]+}}, $5, $4, 2
; CHECK: .size llvm_mips_lsa_test

define i32 @lsa_test(i32 %a, i32 %b) nounwind {
entry:
  %0 = shl i32 %b, 2
  %1 = add i32 %a, %0
  ret i32 %1
}

; CHECK: lsa_test:
; CHECK: lsa {{\$[0-9]+}}, $5, $4, 2
; CHECK: .size lsa_test

Update FileCheck prefix in preparation for the addition of Mips64 tests.

; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.

; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
; RUN:   FileCheck %s --check-prefix=MIPS32

define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
entry:
  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
  ret i32 %0
}

declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind

; MIPS32: llvm_mips_lsa_test:
; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
; MIPS32: .size llvm_mips_lsa_test

define i32 @lsa_test(i32 %a, i32 %b) nounwind {
entry:
  %0 = shl i32 %b, 2
  %1 = add i32 %a, %0
  ret i32 %1
}

; MIPS32: lsa_test:
; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
; MIPS32: .size lsa_test


; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64

; Ensure we access the local stack properly

; PTX32:        mov.u32         %r{{[0-9]+}}, __local_depot{{[0-9]+}};
; PTX32:        cvta.local.u32  %SP, %r{{[0-9]+}};
; PTX32:        ld.param.u32    %r{{[0-9]+}}, [foo_param_0];
; PTX32:        st.u32  [%SP+0], %r{{[0-9]+}};
; PTX64:        mov.u64         %rl{{[0-9]+}}, __local_depot{{[0-9]+}};
; PTX64:        cvta.local.u64  %SP, %rl{{[0-9]+}};
; PTX64:        ld.param.u32    %r{{[0-9]+}}, [foo_param_0];
; PTX64:        st.u32  [%SP+0], %r{{[0-9]+}};
define void @foo(i32 %a) {
  %local = alloca i32, align 4
  store i32 %a, i32* %local
  ret void
}

Fix the test: DCE optimized away everything.

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64

; Ensure we access the local stack properly

; PTX32:        mov.u32          %r{{[0-9]+}}, __local_depot{{[0-9]+}};
; PTX32:        cvta.local.u32   %SP, %r{{[0-9]+}};
; PTX32:        ld.param.u32     %r{{[0-9]+}}, [foo_param_0];
; PTX32:        st.volatile.u32  [%SP+0], %r{{[0-9]+}};
; PTX64:        mov.u64          %rl{{[0-9]+}}, __local_depot{{[0-9]+}};
; PTX64:        cvta.local.u64   %SP, %rl{{[0-9]+}};
; PTX64:        ld.param.u32     %r{{[0-9]+}}, [foo_param_0];
; PTX64:        st.volatile.u32  [%SP+0], %r{{[0-9]+}};
define void @foo(i32 %a) {
  %local = alloca i32, align 4
  store volatile i32 %a, i32* %local
  ret void
}


; RUN: llc < %s -march=x86 | FileCheck %s

; Previously we would forget to align to stack slot alignment after placing a
; byval argument.  Subsequent arguments would align themselves, but if it was
; the last argument, the argument size would not be a multiple of stack slot
; size. This resulted in retl $6 in callee-cleanup functions, as well as subtle
; varargs bugs.

%struct.Six = type { [6 x i8] }

define x86_stdcallcc void @f(%struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: _f@8:
; CHECK: retl $8

define x86_thiscallcc void @g(i8* %this, %struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: _g:
; CHECK: retl $8

define x86_fastcallcc void @h(i32 inreg %x, i32 inreg %y, %struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: @h@8:
; CHECK: retl $8

Add a triple to this test to get the right IR mangling

; RUN: llc < %s -mtriple=i686-win32 | FileCheck %s

; Previously we would forget to align to stack slot alignment after placing a
; byval argument.  Subsequent arguments would align themselves, but if it was
; the last argument, the argument size would not be a multiple of stack slot
; size. This resulted in retl $6 in callee-cleanup functions, as well as subtle
; varargs bugs.

%struct.Six = type { [6 x i8] }

define x86_stdcallcc void @f(%struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: _f@8:
; CHECK: retl $8

define x86_thiscallcc void @g(i8* %this, %struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: _g:
; CHECK: retl $8

define x86_fastcallcc void @h(i32 inreg %x, i32 inreg %y, %struct.Six* byval %a) {
  ret void
}
; CHECK-LABEL: @h@8:
; CHECK: retl $8


; RUN: llvm-as < %s | opt -addreadattrs | llvm-dis | grep readnone | count 2

define i32 @f() {
entry:
	%tmp = call i32 @e( )		; <i32> [#uses=1]
	ret i32 %tmp
}

declare i32 @e() readnone

Add test for improvement of readonly to readnone, and non-demotion of readnone to readonly.

; RUN: llvm-as < %s | opt -addreadattrs | llvm-dis | grep readnone | count 4
@x = global i32 0

declare i32 @e() readnone

define i32 @f() {
	%tmp = call i32 @e( )		; <i32> [#uses=1]
	ret i32 %tmp
}

define i32 @g() readonly {
	ret i32 0
}

define i32 @h() readnone {
	%tmp = load i32* @x		; <i32> [#uses=1]
	ret i32 %tmp
}


; RUN: opt -S -reassociate < %s | FileCheck %s
; rdar://8944681

; Reassociate should clear optional flags like nsw when reassociating.

; CHECK-LABEL: @test0(
; CHECK: %y = add i64 %a, %b
; CHECK: %z = add i64 %c, %y
define i64 @test0(i64 %a, i64 %b, i64 %c) {
  %y = add nsw i64 %c, %b
  %z = add i64 %y, %a
  ret i64 %z
}

; CHECK-LABEL: @test1(
; CHECK: %y = add i64 %a, %b
; CHECK: %z = add i64 %c, %y
define i64 @test1(i64 %a, i64 %b, i64 %c) {
  %y = add i64 %c, %b
  %z = add nsw i64 %y, %a
  ret i64 %z
}

; PR9215
; CHECK: %s = add nsw i32 %x, %y
define i32 @test2(i32 %x, i32 %y) {
  %s = add nsw i32 %x, %y
  ret i32 %s
}

Use test cases that can actually be optimized to verify optional flags are cleared. The reassociation pass was just reordering the leaf nodes in the previous test cases.

; RUN: opt -S -reassociate -dce < %s | FileCheck %s
; rdar://8944681

; Reassociate should clear optional flags like nsw when reassociating.

; CHECK-LABEL: @test0(
; CHECK: %z = add i64 %b, 2
define i64 @test0(i64 %a, i64 %b) {
  %x = add nsw i64 %a, 2
  %y = add nsw i64 %x, %b
  %z = sub nsw i64 %y, %a
  ret i64 %z
}

; CHECK-LABEL: @test1(
; CHECK: %y = mul i64 %a, 6
; CHECK: %z = sub nsw i64 %y, %a
define i64 @test1(i64 %a, i64 %b) {
  %x = add nsw i64 %a, %a
  %y = mul nsw i64 %x, 3
  %z = sub nsw i64 %y, %a
  ret i64 %z
}

; PR9215
; CHECK: %s = add nsw i32 %x, %y
define i32 @test2(i32 %x, i32 %y) {
  %s = add nsw i32 %x, %y
  ret i32 %s
}


; For PR1261. Before bit accurate type support in InstCombine, this would
; turn the sext into a zext.
; RUN: llvm-as %s -o - | opt -instcombine | llvm-dis &&
; RUN: llvm-as %s -o - | opt -instcombine | llvm-dis | not grep zext
; XFAIL: *

define i16 @test(i31 %zzz) {
entry:
  %A = sext i31 %zzz to i32
  %B = add i32 %A, 16384
  %C = lshr i32 %B, 15
  %D = trunc i32 %C to i16
  ret i16 %D
}

Make this test a little simpler/faster.

; For PR1261. Before bit accurate type support in InstCombine, this would
; turn the sext into a zext.
; RUN: llvm-as %s -o - | opt -instcombine | llvm-dis | grep sext
; XFAIL: *

define i16 @test(i31 %zzz) {
entry:
  %A = sext i31 %zzz to i32
  %B = add i32 %A, 16384
  %C = lshr i32 %B, 15
  %D = trunc i32 %C to i16
  ret i16 %D
}


; RUN: llvm-upgrade < %s | llvm-as | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN: diff %t1.ll %t2.ll

  %myty = type int
  %myfn = type float (int,double,uint,short)
  type int(%myfn*)
  type int(int)
  type int(int(int)*)

  %thisfuncty = type int (int) *
implementation

declare void %F(%thisfuncty, %thisfuncty, %thisfuncty)

; This function always returns zero
int %zarro(int %Func)
begin
Startup:
    add int 0, 10
    ret int 0
end

int %test(int)
begin
    call void %F(%thisfuncty %zarro, %thisfuncty %test, %thisfuncty %foozball)
    ret int 0
end

int %foozball(int)
begin
    ret int 0
end

Make sure upgrade doesn't fail on this.

; RUN: llvm-upgrade < %s | llvm-as | llvm-ds -o /dev/null -f &&
; RUN: llvm-upgrade < %s | llvm-as | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN: diff %t1.ll %t2.ll

  %myty = type int
  %myfn = type float (int,double,uint,short)
  type int(%myfn*)
  type int(int)
  type int(int(int)*)

  %thisfuncty = type int (int) *
implementation

declare void %F(%thisfuncty, %thisfuncty, %thisfuncty)

; This function always returns zero
int %zarro(int %Func)
begin
Startup:
    add int 0, 10
    ret int 0
end

int %test(int)
begin
    call void %F(%thisfuncty %zarro, %thisfuncty %test, %thisfuncty %foozball)
    ret int 0
end

int %foozball(int)
begin
    ret int 0
end


; RUN: llvm-as < %s | opt -basicaa -load-vn -gcse -instcombine | llvm-dis | not grep sub

sbyte %test(sbyte** %P) {
	%A = load sbyte** %P
	%B = load sbyte* %A

	%X = load sbyte** %P
	%Y = load sbyte* %X

	%R = sub sbyte %B, %Y
	ret sbyte %R
}

Add another variant of the testcase

; RUN: llvm-as < %s | opt -basicaa -load-vn -gcse -instcombine | llvm-dis | not grep sub

%S = type { int, sbyte }

sbyte %test(sbyte** %P) {
	%A = load sbyte** %P
	%B = load sbyte* %A

	%X = load sbyte** %P
	%Y = load sbyte* %X

	%R = sub sbyte %B, %Y
	ret sbyte %R
}

sbyte %test(%S ** %P) {
	%A = load %S** %P
	%B = getelementptr %S* %A, int 0, ubyte 1
	%C = load sbyte* %B

	%X = load %S** %P
	%Y = getelementptr %S* %X, int 0, ubyte 1
	%Z = load sbyte* %Y

	%R = sub sbyte %C, %Z
	ret sbyte %R
}


; RUN: llc < %s -march=x86  | FileCheck %s

define zeroext i8 @t(double %x) nounwind readnone {
entry:
	%0 = fptosi double %x to i32		; <i32> [#uses=1]
	%1 = sitofp i32 %0 to double		; <double> [#uses=1]
	%2 = fcmp oeq double %1, %x		; <i1> [#uses=1]
	%retval12 = zext i1 %2 to i8		; <i8> [#uses=1]
; CHECK: cmpeqsd
	ret i8 %retval12
}

define zeroext i8 @u(double %x) nounwind readnone {
entry:
	%0 = fptosi double %x to i32		; <i32> [#uses=1]
	%1 = sitofp i32 %0 to double		; <double> [#uses=1]
	%2 = fcmp une double %1, %x		; <i1> [#uses=1]
	%retval12 = zext i1 %2 to i8		; <i8> [#uses=1]
; CHECK: cmpneqsd
	ret i8 %retval12
}

Tweak testcase for ARM bot. rdar://problem/5993888

; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s

define zeroext i8 @t(double %x) nounwind readnone {
entry:
	%0 = fptosi double %x to i32		; <i32> [#uses=1]
	%1 = sitofp i32 %0 to double		; <double> [#uses=1]
	%2 = fcmp oeq double %1, %x		; <i1> [#uses=1]
	%retval12 = zext i1 %2 to i8		; <i8> [#uses=1]
; CHECK: cmpeqsd
	ret i8 %retval12
}

define zeroext i8 @u(double %x) nounwind readnone {
entry:
	%0 = fptosi double %x to i32		; <i32> [#uses=1]
	%1 = sitofp i32 %0 to double		; <double> [#uses=1]
	%2 = fcmp une double %1, %x		; <i1> [#uses=1]
	%retval12 = zext i1 %2 to i8		; <i8> [#uses=1]
; CHECK: cmpneqsd
	ret i8 %retval12
}


; RUN: opt -gvn -S < %s | FileCheck %s

declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8)

define void @foo(i8* %ptr) {
  %P = getelementptr i8* %ptr, i32 0
  %Q = getelementptr i8* %ptr, i32 1
; CHECK: getelementptr
  %X = load i8* %P
; CHECK: = load
  %Y = call i8 @llvm.atomic.load.add.i8.p0i8(i8* %Q, i8 1)
  %Z = load i8* %P
; CHECK-NOT: = load
  ret void
; CHECK: ret void
}

Make use of the result of the loads even though that means adding -instcombine.

; RUN: opt -gvn -instcombine -S < %s | FileCheck %s

declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8)

define i8 @foo(i8* %ptr) {
  %P = getelementptr i8* %ptr, i32 0
  %Q = getelementptr i8* %ptr, i32 1
; CHECK: getelementptr
  %X = load i8* %P
  %Y = call i8 @llvm.atomic.load.add.i8.p0i8(i8* %Q, i8 1)
  %Z = load i8* %P
; CHECK-NOT: = load
  %A = sub i8 %X, %Z
  ret i8 %A
; CHECK: ret i8 0
}


; RUN: not llc -march=x86 -filetype=obj < %s 2>&1 -o /dev/null | FileCheck %s

module asm ".word 0x10"
module asm ".word -bar"

; CHECK: <inline asm>:2:7: error: expected relocatable expression

module asm ".word -foo"
; CHECK: <inline asm>:3:7: error: expected relocatable expression

Fix inline asm diagnostics test.

; RUN: not llc -filetype=obj < %s 2>&1 -o /dev/null | FileCheck %s

module asm ".word 0x10"
module asm ".word -bar"

; CHECK: <inline asm>:2:{{[0-9]+}}: error: expected relocatable expression

module asm ".word -foo"
; CHECK: <inline asm>:3:{{[0-9]+}}: error: expected relocatable expression


; RUN: llvm-as < %s | llc -march=x86 | not grep 4294967289
; RUN: llvm-as < %s | llc -march=x86 | grep 4294967280
; RUN: llvm-as < %s | llc -march=x86-64 | grep {\\-16}

define void @t() {
A:
	br label %entry

entry:
	%m1 = alloca i32, align 4
	%m2 = alloca [7 x i8], align 16
	call void @s( i32* %m1, [7 x i8]* %m2 )
	ret void
}

declare void @s(i32*, [7 x i8]*)

Update this test for recent codegen improvements. CodeGen is now using an lea in place of a mov and an add for this test.

; RUN: llvm-as < %s | llc -march=x86 | not egrep {\$4294967289|-7\\(}
; RUN: llvm-as < %s | llc -march=x86 | egrep {\$4294967280|-16\\(}
; RUN: llvm-as < %s | llc -march=x86-64 | grep {\\-16}

define void @t() {
A:
	br label %entry

entry:
	%m1 = alloca i32, align 4
	%m2 = alloca [7 x i8], align 16
	call void @s( i32* %m1, [7 x i8]* %m2 )
	ret void
}

declare void @s(i32*, [7 x i8]*)


; RUN: llc < %s -mcpu=corei7-avx | FileCheck %s

; Make sure that we are not generating a movaps because the vector is aligned to 1.
;CHECK: @foo
;CHECK: xor
;CHECK-NEXT: vmovups
;CHECK-NEXT: ret
define void @foo() {
  store <16 x i16> zeroinitializer, <16 x i16>* undef, align 1
  ret void
}

Add a triple to the test.

; RUN: llc < %s -mcpu=corei7-avx | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"

; Make sure that we are not generating a movaps because the vector is aligned to 1.
;CHECK: @foo
;CHECK: xor
;CHECK-NEXT: vmovups
;CHECK-NEXT: ret
define void @foo() {
  store <16 x i16> zeroinitializer, <16 x i16>* undef, align 1
  ret void
}


; This test makes sure that these instructions are properly eliminated.
;

; RUN: if as < %s | opt -instcombine -die | dis | grep phi
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

implementation

int %test1(int %A, bool %b) {
BB0:    br bool %b, label %BB1, label %BB2
BB1:
        %B = phi int [%A, %BB0]     ; Combine away one argument PHI nodes
        ret int %B
BB2:
        ret int %A
}

int %test2(int %A, bool %b) {
BB0:    br bool %b, label %BB1, label %BB2
BB1:
	br label %BB2
BB2:
        %B = phi int [%A, %BB0], [%A, %BB1]     ; Combine away PHI nodes with same values
        ret int %B
}

Add new testcases for instcombine

; This test makes sure that these instructions are properly eliminated.
;

; RUN: if as < %s | opt -instcombine -die | dis | grep phi
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

implementation

int %test1(int %A, bool %b) {
BB0:    br bool %b, label %BB1, label %BB2
BB1:
        %B = phi int [%A, %BB0]     ; Combine away one argument PHI nodes
        ret int %B
BB2:
        ret int %A
}

int %test2(int %A, bool %b) {
BB0:    br bool %b, label %BB1, label %BB2
BB1:
	br label %BB2
BB2:
        %B = phi int [%A, %BB0], [%A, %BB1]     ; Combine away PHI nodes with same values
        ret int %B
}

int %test3(int %A, bool %b) {
BB0: br label %Loop

Loop:
	%B = phi int [%A, %BB0], [%B, %Loop]    ; PHI has same value always.
	br bool %b, label %Loop, label %Exit
Exit:
	ret int %B
}

int %test3(bool %b) {
BB0:  ret int 7                                 ; Loop is unreachable

Loop:
        %B = phi int [%B, %L2], [%B, %Loop]     ; PHI has same value always.
        br bool %b, label %L2, label %Loop
L2:
	br label %Loop
}


; This testcase checks to see if the simplifycfg pass is converting invoke
; instructions to call instructions if the handler just rethrows the exception.

; If this test is successful, the function should be reduced to 'call; ret'

; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not egrep 'invoke|br'

declare void %bar()
declare void %llvm.unwind()

int %test() {
	invoke void %bar() to label %Ok except label %Rethrow
Ok:
	ret int 0
Rethrow:
	call void %llvm.unwind()
	br label %Ok
}

Fix testcase. For some reason this was failing only with a release build and not with a debug build? Rather testrunner only caught it in that case.

; This testcase checks to see if the simplifycfg pass is converting invoke
; instructions to call instructions if the handler just rethrows the exception.

; If this test is successful, the function should be reduced to 'call; ret'

; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not egrep 'invoke|br'

declare void %bar()

int %test() {
	invoke void %bar() to label %Ok except label %Rethrow
Ok:
	ret int 0
Rethrow:
	unwind
}


; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 2

define i64 @a(i32 %a, i32 %b) nounwind readnone {
entry:
	%0 = insertelement <2 x i32> undef, i32 %a, i32 0		; <<2 x i32>> [#uses=1]
	%1 = insertelement <2 x i32> %0, i32 %b, i32 1		; <<2 x i32>> [#uses=1]
	%conv = bitcast <2 x i32> %1 to i64		; <i64> [#uses=1]
	ret i64 %conv
}

Stabilize the test by specifying an exact cpu target

; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -mattr=+mmx | grep movd | count 2

define i64 @a(i32 %a, i32 %b) nounwind readnone {
entry:
	%0 = insertelement <2 x i32> undef, i32 %a, i32 0		; <<2 x i32>> [#uses=1]
	%1 = insertelement <2 x i32> %0, i32 %b, i32 1		; <<2 x i32>> [#uses=1]
	%conv = bitcast <2 x i32> %1 to i64		; <i64> [#uses=1]
	ret i64 %conv
}


; RUN: opt -globalopt %s -S -o - | FileCheck %s
; PR10047

%0 = type { i32, void ()* }
%struct.A = type { [100 x i32] }

; CHECK: @a
@a = global %struct.A zeroinitializer, align 4
@llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I_a }]

declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind

; CHECK-NOT: GLOBAL__I_a
define internal void @_GLOBAL__I_a() nounwind {
entry:
  tail call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.A* @a to i8*), i8 0, i64 400, i32 4, i1 false) nounwind
  ret void
}

Add testcase for r132290, to check for the crasher caught by the buildbots doing llvm-gcc selfhost (or cross).

; RUN: opt -globalopt %s -S -o - | FileCheck %s
; PR10047

%0 = type { i32, void ()* }
%struct.A = type { [100 x i32] }

; CHECK: @a
@a = global %struct.A zeroinitializer, align 4
@llvm.global_ctors = appending global [2 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I_a }, %0 { i32 65535, void ()* @_GLOBAL__I_b }]

declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind

; CHECK-NOT: GLOBAL__I_a
define internal void @_GLOBAL__I_a() nounwind {
entry:
  tail call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.A* @a to i8*), i8 0, i64 400, i32 4, i1 false) nounwind
  ret void
}

%struct.X = type { i8 }
@y = global i8* null, align 8
@x = global %struct.X zeroinitializer, align 1

define internal void @_GLOBAL__I_b() nounwind {
entry:
  %tmp.i.i.i = load i8** @y, align 8
  tail call void @llvm.memset.p0i8.i64(i8* %tmp.i.i.i, i8 0, i64 10, i32 1, i1 false) nounwind
  ret void
}


; RUN: llc -march=x86 -align-all-blocks=16 < %s | FileCheck %s

;CHECK: foo
;CHECK: .align  16, 0x90
;CHECK: .align  16, 0x90
;CHECK: .align  16, 0x90
;CHECK: ret
define i32 @foo(i32 %t, i32 %l) nounwind readnone ssp uwtable {
  %1 = icmp eq i32 %t, 0
  br i1 %1, label %4, label %2

; <label>:2                                       ; preds = %0
  %3 = add nsw i32 %t, 2
  ret i32 %3

; <label>:4                                       ; preds = %0
  %5 = icmp eq i32 %l, 0
  %. = select i1 %5, i32 0, i32 5
  ret i32 %.
}

Fix the test on linux by setting the triple and the align format

; RUN: llc  -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s

;CHECK: foo
;CHECK: .align  65536, 0x90
;CHECK: .align  65536, 0x90
;CHECK: .align  65536, 0x90
;CHECK: ret
define i32 @foo(i32 %t, i32 %l) nounwind readnone ssp uwtable {
  %1 = icmp eq i32 %t, 0
  br i1 %1, label %4, label %2

; <label>:2                                       ; preds = %0
  %3 = add nsw i32 %t, 2
  ret i32 %3

; <label>:4                                       ; preds = %0
  %5 = icmp eq i32 %l, 0
  %. = select i1 %5, i32 0, i32 5
  ret i32 %.
}


; RUN: llvm-upgrade < %s | llvm-as | llc -march=c

declare int %callee(int, int)

int %test(int %X) {
	%A = invoke int %callee(int %X, int 5) to label %Ok except label %Threw
Ok:
	%B = phi int [%A, %0], [-1, %Threw]
	ret int %A
Threw:
	br label %Ok
}

Fix one more broken testcase

; RUN: llvm-upgrade < %s | llvm-as | llc -march=c

declare int %callee(int, int)

int %test(int %X) {
	%A = invoke int %callee(int %X, int 5) to label %Ok except label %Threw
Ok:
	%B = phi int [%A, %0], [-1, %Threw]
	ret int %B
Threw:
	br label %Ok
}


; RUN: opt -module-summary %s -o %t.o
; RUN: llvm-cat -b -o %t2.o %t.o %t.o
; RUN: not llvm-lto2 -o %t3.o %t2.o 2>&1 | FileCheck %s
; CHECK: Expected at most one ThinLTO module per bitcode file

target triple = "x86_64-unknown-linux-gnu"

Add the missing datalayout in a test.

; RUN: opt -module-summary %s -o %t.o
; RUN: llvm-cat -b -o %t2.o %t.o %t.o
; RUN: not llvm-lto2 -o %t3.o %t2.o 2>&1 | FileCheck %s
; CHECK: Expected at most one ThinLTO module per bitcode file

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"


; RUN: llvm-as %s -o - | opt -instcombine

	%struct.llvm_java_object_base = type opaque
	"java/lang/Object" = type { %struct.llvm_java_object_base }
	"java/lang/StringBuffer" = type { "java/lang/Object", int, { "java/lang/Object", uint, [0 x ushort] }*, bool }

implementation   ; Functions:

void "java/lang/StringBuffer/append(Ljava/lang/String;)Ljava/lang/StringBuffer;"() {
bc0:
	%tmp53 = getelementptr "java/lang/StringBuffer"* null, int 0, uint 1		; <int*> [#uses=1]
	store int 0, int* %tmp53
	ret void
}

Mark this as an XFAIL until a fix is worked out.

; RUN: llvm-as %s -o - | opt -instcombine
; XFAIL: *

	%struct.llvm_java_object_base = type opaque
	"java/lang/Object" = type { %struct.llvm_java_object_base }
	"java/lang/StringBuffer" = type { "java/lang/Object", int, { "java/lang/Object", uint, [0 x ushort] }*, bool }

implementation   ; Functions:

void "java/lang/StringBuffer/append(Ljava/lang/String;)Ljava/lang/StringBuffer;"() {
bc0:
	%tmp53 = getelementptr "java/lang/StringBuffer"* null, int 0, uint 1		; <int*> [#uses=1]
	store int 0, int* %tmp53
	ret void
}


; RUN: llvm-as < %s | llc -march=x86
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 | grep {array,16512,7}
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep {array,16512,7}
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin8 | not grep {7}

; Darwin 9+ should get alignment on common symbols.  Darwin8 does
; not support this.
@array = weak global [4128 x i32] zeroinitializer, align 128

Use common where we mean common, not weak.

; RUN: llvm-as < %s | llc -march=x86
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin10 | grep {array,16512,7}
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 | grep {array,16512,7}
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin8 | not grep {7}

; Darwin 9+ should get alignment on common symbols.  Darwin8 does
; not support this.
@array = common global [4128 x i32] zeroinitializer, align 128


; RUN: opt < %s -extract-blocks -disable-output
define i32 @foo() {
        br label %EB

EB:             ; preds = %0
        %V = invoke i32 @foo( )
                        to label %Cont unwind label %Unw                ; <i32> [#uses=1]

Cont:           ; preds = %EB
        ret i32 %V

Unw:            ; preds = %EB
        unwind
}

Update test to remove the 'unwind' instruction.

; RUN: opt < %s -extract-blocks -disable-output
define i32 @foo() {
        br label %EB

EB:             ; preds = %0
        %V = invoke i32 @foo( )
                        to label %Cont unwind label %Unw                ; <i32> [#uses=1]

Cont:           ; preds = %EB
        ret i32 %V

Unw:            ; preds = %EB
        %exn = landingpad {i8*, i32} personality i32 (...)* @__gcc_personality_v0
                 catch i8* null
        resume { i8*, i32 } %exn
}

declare i32 @__gcc_personality_v0(...)


; RUN: opt -loop-load-elim -S < %s | FileCheck %s

; Don't crash if the store and the load use different types.
;
;   for (unsigned i = 0; i < 100; i++) {
;     A[i+1] = B[i] + 2;
;     C[i] = ((float*)A)[i] * 2;
;   }

target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"

define void @f(i32* noalias %A, i32* noalias %B, i32* noalias %C, i64 %N) {

entry:
  br label %for.body

for.body:                                         ; preds = %for.body, %entry
  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1

  %Aidx_next = getelementptr inbounds i32, i32* %A, i64 %indvars.iv.next
  %Bidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
  %Cidx = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
  %Aidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
  %Aidx.float = bitcast i32* %Aidx to float*

  %b = load i32, i32* %Bidx, align 4
  %a_p1 = add i32 %b, 2
  store i32 %a_p1, i32* %Aidx_next, align 4

; CHECK: %a = load float, float* %Aidx.float, align 4
  %a = load float, float* %Aidx.float, align 4
; CHECK-NEXT: %c = fmul float %a, 2.0
  %c = fmul float %a, 2.0
  %c.int = fptosi float %c to i32
  store i32 %c.int, i32* %Cidx, align 4

  %exitcond = icmp eq i64 %indvars.iv.next, %N
  br i1 %exitcond, label %for.end, label %for.body

for.end:                                          ; preds = %for.body
  ret void
}


; REQUIRES: x86
; RUN: llvm-as %s -o %t1.o
; RUN: not ld.lld -o %t %t1.o 2>&1 | FileCheck %s

; CHECK: undefined symbol: foobar

; We used to crash setting foobar to non-dso_local

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@foobar = external hidden global i32
define i32* @_start() {
  ret i32* @foobar
}


Add another test case which tests Mips' unaligned load/store instructions.

; RUN: llc -march=mipsel < %s | FileCheck  -check-prefix=EL %s
; RUN: llc -march=mips < %s | FileCheck  -check-prefix=EB %s

%struct.SI = type { i32 }

@si = common global %struct.SI zeroinitializer, align 1

define i32 @foo_load_i() nounwind readonly {
entry:
; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
; EL: lwr $[[R0]], 0($[[R1]])
; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
; EB: lwr $[[R0]], 3($[[R1]])

  %0 = load i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1
  ret i32 %0
}

define void @foo_store_i(i32 %a) nounwind {
entry:
; EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
; EL: swr $[[R0]], 0($[[R1]])
; EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
; EB: swr $[[R0]], 3($[[R1]])

  store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1
  ret void
}


Add a new test case for the llvm.memcpy simplification case.

; Test that the StrCatOptimizer works correctly
; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | not grep 'call.*llvm.memcpy'

declare sbyte* %llvm.memcpy(sbyte*,sbyte*,int,int)
%h = constant [2 x sbyte] c"h\00"
%hel = constant [4 x sbyte] c"hel\00"
%hello_u = constant [8 x sbyte] c"hello_u\00"

implementation   ; Functions:

int %main () {
  %h_p = getelementptr [2 x sbyte]* %h, int 0, int 0
  %hel_p = getelementptr [4 x sbyte]* %hel, int 0, int 0
  %hello_u_p = getelementptr [8 x sbyte]* %hello_u, int 0, int 0
  %target = alloca [1024 x sbyte]
  %target_p = getelementptr [1024 x sbyte]* %target, int 0, int 0
  call sbyte* %llvm.memcpy(sbyte* %target_p, sbyte* %h_p, int 2, int 2)
  call sbyte* %llvm.memcpy(sbyte* %target_p, sbyte* %hel_p, int 4, int 4)
  call sbyte* %llvm.memcpy(sbyte* %target_p, sbyte* %hello_u_p, int 8, int 8)
  ret int 0
}


Fix miscompilation found in Fhourstones by bugpoint

; This testcase tests for a problem where LICM hoists loads out of a loop
; despite the fact that calls to unknown functions may modify what is being
; loaded from.  Basically if the load gets hoisted, the subtract gets turned
; into a constant zero.
;
; RUN: as < %s | opt -licm -load-vn -gcse -instcombine | llvm-dis | grep load

%X = global int 7
declare void %foo()

int %test(bool %c) {
	%A = load int *%X
	br label %Loop
Loop:
	call void %foo()
	%B = load int *%X  ;; Should not hoist this load!
	br bool %c, label %Loop, label %Out
Out:
	%C = sub int %A, %B
	ret int %C
}


Add test for merging of min-legal-vector-width function attribute.

; RUN: opt %s -inline -S | FileCheck %s

define internal void @innerSmall() "min-legal-vector-width"="128" {
  ret void
}

define internal void @innerLarge() "min-legal-vector-width"="512" {
  ret void
}

define void @outerNoAttribute() {
  call void @innerLarge()
  ret void
}

define void @outerConflictingAttributeSmall() "min-legal-vector-width"="128" {
  call void @innerLarge()
  ret void
}

define void @outerConflictingAttributeLarge() "min-legal-vector-width"="512" {
  call void @innerSmall()
  ret void
}

; CHECK: define void @outerNoAttribute() #0
; CHECK: define void @outerConflictingAttributeSmall() #0
; CHECK: define void @outerConflictingAttributeLarge() #0
; CHECK: attributes #0 = { "min-legal-vector-width"="512" }


Make all the schedulers continue to work.

; RUN: llvm-as -f %s -o - | llc -sched=none
; RUN: llvm-as -f %s -o - | llc -sched=default
; RUN: llvm-as -f %s -o - | llc -sched=simple
; RUN: llvm-as -f %s -o - | llc -sched=simple-noitin
; RUN: llvm-as -f %s -o - | llc -sched=list-td
; RUN: llvm-as -f %s -o - | llc -sched=list-tdrr
; RUN: llvm-as -f %s -o - | llc -sched=list-burr
; PR859

implementation
declare int "printf"(sbyte*, int, float)

int "testissue"(int %i, float %x, float %y)
begin
	br label %bb1
bb1:
	%x1 = mul float %x, %y			;; x1
	%y1 = mul float %y, 0.75		;; y1
	%z1 = add float %x1, %y1		;; z1 = x1 + y1

	%x2 = mul float %x, 0.5			;; x2
	%y2 = mul float %y, 0.9			;; y2
	%z2 = add float %x2, %y2		;; z2 = x2 + y2

	%z3 = add float %z1, %z2		;; z3 = z1 + z2

	%i1 = shl int   %i, ubyte 3		;; i1
	%j1 = add int   %i, 7			;; j1
	%m1 = add int   %i1, %j1		;; k1 = i1 + j1
;;	%m1 = div int   %k1, 99			;; m1 = k1 / 99

	%b  = setle int %m1, 6			;; (m1 <= 6)?
	br bool %b, label %bb1, label %bb2

bb2:
	%Msg = cast ulong 0 to sbyte *
	call int %printf(sbyte* %Msg, int %m1, float %z3)
	ret int 0
end


Add ppc-specific test for better i64 compare codegen.

; RUN: llvm-as < %s | llc -march=ppc32 | grep cntlzw &&
; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori &&
; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'li ' &&
; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'mr '

define i1 @test(i64 %x) {
  %tmp = icmp ult i64 %x, 4294967296
  ret i1 %tmp
}


Add test case to show that we don't set the kill flag properly for fast isel handling of fneg.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=expand-isel-pseudos | FileCheck %s

; Make sure we output the right kill flag for the xor conversion.

define void @goo(double* %x, double* %y) nounwind {
; CHECK: %[[REG2:.*]]:gr64 = COPY $rsi
; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi
; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]]
; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]]
; CHECK-NEXT: %[[REG10:.*]]:fr64 = MOVSDrm %[[REG1]], 1, $noreg, 0, $noreg :: (load 8 from %ir.x)
; CHECK-NEXT: %[[REG6:.*]]:gr64 = MOVSDto64rr %[[REG10]]
; CHECK-NEXT: %[[REG7:.*]]:gr64 = MOV64ri -9223372036854775808
; CHECK-NEXT: %[[REG8:.*]]:gr64 = XOR64rr killed %[[REG6]], %[[REG7]], implicit-def $eflags
; CHECK-NEXT: %[[REG9:.*]]:fr64 = MOV64toSDrr killed %[[REG8]]
; CHECK-NEXT: MOVSDmr %[[REG3]], 1, $noreg, 0, $noreg, killed %[[REG9]] :: (store 8 into %ir.y)
; CHECK-NEXT: RETQ
  %a = load double, double* %x
  %b = fsub double -0.0, %a
  store double %b, double* %y
  ret void
}


; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs
; XFAIL: *

; An undef argument causes a setugt node to escape instruction selection.

define void @bugt() {
cond_next305:
  %tmp306307 = trunc i32 undef to i8              ; <i8> [#uses=1]
  %tmp308 = icmp ugt i8 %tmp306307, 6             ; <i1> [#uses=1]
  br i1 %tmp308, label %bb311, label %bb314

bb311:                                            ; preds = %cond_next305
  unreachable

bb314:                                            ; preds = %cond_next305
  ret void
}


Add testcase to make sure we don't generate too many jumps for a une compare. <rdar://problem/7859988>

; RUN: llc < %s -march=x86 -mattr=sse4.1 | FileCheck %s
; <rdar://problem/7859988>

; Make sure we don't generate more jumps than we need to. We used to generate
; something like this:
;
;       jne  LBB0_1
;       jnp  LBB0_2
;   LBB0_1:
;       jmp  LBB0_3
;   LBB0_2:
;       addsd ...
;   LBB0_3:
;
; Now we generate this:
;
;       jne  LBB0_2
;       jp   LBB0_2
;       addsd ...
;   LBB0_2:

; CHECK:       func
; CHECK:       jne [[LABEL:.*]]
; CHECK-NEXT:  jp  [[LABEL]]
; CHECK-NOT:   jmp

define float @func(float %x, float %y) nounwind readnone optsize ssp {
entry:
  %0 = fpext float %x to double
  %1 = fpext float %y to double
  %2 = fmul double %0, %1
  %3 = fcmp une double %2, 0.000000e+00
  br i1 %3, label %bb2, label %bb1

bb1:
  %4 = fadd double %2, -1.000000e+00
  br label %bb2

bb2:
  %.0.in = phi double [ %4, %bb1 ], [ %2, %entry ]
  %.0 = fptrunc double %.0.in to float
  ret float %.0
}


Add test to show up we don't support ThinLTO yet.

; RUN: opt -module-summary %s -o %t1.bc
; RUN: not llvm-lto2 %t1.bc -o %t.o \
; RUN:     -r=%t1.bc,_tinkywinky,pxl \
; RUN:     -lto-use-new-pm 2>&1 | FileCheck %s

; CHECK: ThinLTO not supported with the new PM yet!

target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0"

define void @tinkywinky() {
    ret void
}


Add a test case for a particular udiv/select transform.

; This tests that this transform:
; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
;
; RUN: llvm-as %s -o - | opt -instcombine | llvm-dis -f -o %t && \
; RUN:   grep select %t | wc -l | grep 1 && \
; RUN:   grep lshr %t | wc -l | grep 2 && \
; RUN:   grep udiv %t | wc -l | grep 0

define i64 @test(i64 %X, i1 %Cond ) {
entry:
        %divisor1 = select i1 %Cond, i64 8, i64 16
        %quotient1 = udiv i64 %X, %divisor1
        %divisor2 = select i1 %Cond, i64 8, i64 0
        %quotient2 = udiv i64 %X, %divisor2
        %sum = add i64 %quotient1, %quotient2
        ret i64 %sum
}


Test case for r140670: indvars should hoist sext.

; RUN: opt < %s -indvars -S | FileCheck %s
; Test indvars' ability to hoist new sext created by WidenIV.
; From ffbench.

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
define internal double @fourn(double* %data, i32 %x, i32 %y, i32 %n) nounwind {
; CHECK: entry:
; CHECK: sext
; CHECK: sext
entry:
  br label %for.body

; CHECK: for.body:
; CHECK-NOT: sext
; CHECK: br
for.body:
  %i2.115 = phi i32 [ 0, %entry ], [ %add249, %for.body ]
  %add174 = add nsw i32 %i2.115, %x
  %idxprom177 = sext i32 %add174 to i64
  %arrayidx179 = getelementptr inbounds double* %data, i64 %idxprom177
  %tmp180 = load double* %arrayidx179, align 8
  %add249 = add nsw i32 %i2.115, %y
  %cmp168 = icmp sgt i32 %add249, %n
  br i1 %cmp168, label %exit, label %for.body

exit:
  ret double %tmp180
}


Add failing testcase reduced from OpenCV

; XFAIL: *
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s

define void @init_data_cost_reduce_0(i32 %arg) #0 {
bb:
  br i1 undef, label %bb1, label %bb2

bb1:                                              ; preds = %bb
  br label %bb2

bb2:                                              ; preds = %bb1, %bb
  br i1 undef, label %bb3, label %bb4

bb3:                                              ; preds = %bb2
  %tmp = mul i32 undef, %arg
  br label %bb4

bb4:                                              ; preds = %bb3, %bb2
  unreachable
}

attributes #0 = { nounwind }


Make sure that LCSSA works properly when it encounters an exit block that has more than one predecessor inside the loop.

; RUN: llvm-as < %s | opt -lcssa | llvm-dis | grep "%X.1.lcssa" &&
; RUN: llvm-as < %s | opt -lcssa | llvm-dis | not grep "%X.1.lcssa1"

declare bool %c1()
declare bool %c2()

int %foo() {
entry:
  br label %loop_begin

loop_begin:
  br bool true, label %loop_body.1, label %loop_exit2

loop_body.1:
  %X.1 = add int 0, 1
  %rel.1 = call bool %c1()
  br bool %rel.1, label %loop_exit, label %loop_body.2

loop_body.2:
  %rel.2 = call bool %c2()
  br bool %rel.2, label %loop_exit, label %loop_begin

loop_exit:
  ret int %X.1

loop_exit2:
  ret int 1
}


Add a testcase that checks that we generate functions with frame pointers or not depending upon the function attributes.

; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s

define void @bar(i32 %argc) #0 {
; CHECK: bar:
; CHECK: pushq %rbp
entry:
  %conv = sitofp i32 %argc to double
  %mul = fmul double %conv, 3.792700e+01
  %conv1 = fptrunc double %mul to float
  %div = fdiv double 9.273700e+02, %conv
  %conv3 = fptrunc double %div to float
  tail call void @foo(float %conv1, float %conv3)
  ret void
}

define void @qux(i32 %argc) #1 {
; CHECK: qux:
; CHECK-NOT: pushq %rbp
entry:
  %conv = sitofp i32 %argc to double
  %mul = fmul double %conv, 3.792700e+01
  %conv1 = fptrunc double %mul to float
  %div = fdiv double 9.273700e+02, %conv
  %conv3 = fptrunc double %div to float
  tail call void @foo(float %conv1, float %conv3)
  ret void
}

declare void @foo(float, float)

attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }


Add test for PR1996. (This is my first time adding a test for a transform, so please review.)

; RUN: llvm-as < %s | opt -gvn | llvm-dis | not grep load

%struct.anon = type { i32, i8, i8, i8, i8 }

define i32 @a() {
entry:
        %c = alloca %struct.anon                ; <%struct.anon*> [#uses=2]
        %tmp = getelementptr %struct.anon* %c, i32 0, i32 0             ; <i32*> [#uses=1]
        %tmp1 = getelementptr i32* %tmp, i32 1          ; <i32*> [#uses=2]
        %tmp2 = load i32* %tmp1, align 4                ; <i32> [#uses=1]
        %tmp3 = or i32 %tmp2, 11                ; <i32> [#uses=1]
        %tmp4 = and i32 %tmp3, -21              ; <i32> [#uses=1]
        store i32 %tmp4, i32* %tmp1, align 4
        %call = call i32 (...)* @x( %struct.anon* %c )          ; <i32> [#uses=0]
        ret i32 undef
}

declare i32 @x(...)


Test that the eh lowering code can handle constant folded bitcasts.

; RUN: llvm-as < %s | llc -enable-eh

	%struct.exception = type { i8, i8, i32, i8*, i8*, i32, i8* }
@program_error = external global %struct.exception		; <%struct.exception*> [#uses=1]

define void @typeinfo() {
entry:
	%eh_typeid = tail call i32 @llvm.eh.typeid.for( i8* getelementptr (%struct.exception* @program_error, i32 0, i32 0) )		; <i32> [#uses=0]
	ret void
}

declare i32 @llvm.eh.typeid.for(i8*)


Add a test case for testing the LLI interpreter wrt bitcast of fp to integer.

; RUN: llvm-as < %s > %t.bc
; RUN: lli -force-interpreter=true %t.bc | grep 40091eb8
;
define i32 @test(double %x) {
entry:
	%x46.i = bitcast double %x to i64
	%tmp343.i = lshr i64 %x46.i, 32
	%tmp344.i = trunc i64 %tmp343.i to i32
        ret i32 %tmp344.i
}

define i32 @main()
{
       %res = call i32 @test(double 3.14)
       %ptr = getelementptr [4 x i8]* @format, i32 0, i32 0
       call i32 (i8*,...)* @printf(i8* %ptr, i32 %res)
       ret i32 0
}

declare i32 @printf(i8*, ...)
@format = internal constant [4 x i8] c"%x\0A\00"


Add testcase for PR3168. It was fixed over time. PR3168

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; PR3168

; CHECK-LABEL: append

define i32* @append() gc "ocaml" {
entry:
  switch i32 0, label %L2 [i32 0, label %L1]
L1:
  %var8 = alloca i8*
  call void @llvm.gcroot(i8** %var8,i8* null)
  br label %L3
L2:
  call ccc void @oread_runtime_casenotcovered()
  unreachable
L3:
  ret i32* null
}

declare ccc void @oread_runtime_casenotcovered()
declare void @llvm.gcroot(i8**,i8*)


; RUN:  llc -O3 -code-model=default -relocation-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s
; Check that we respect the existing chain between loads and stores when we
; legalize unaligned loads.
; Test case from PR24669.

; Make sure the loads happen before the stores.
; CHECK-LABEL: get_set_complex:
; CHECK-NOT: str
; CHECK: ldr
; CHECK-NOT: str
; CHECK: ldr
; CHECK: str
; CHECK: bx
define i32 @get_set_complex({ float, float }* noalias nocapture %retptr,
                            { i8*, i32 }** noalias nocapture readnone %excinfo,
                            i8* noalias nocapture readnone %env,
                            [38 x i8]* nocapture %arg.rec,
                            float %arg.val.0, float %arg.val.1)
{
entry:
  %inserted.real = insertvalue { float, float } undef, float %arg.val.0, 0
  %inserted.imag = insertvalue { float, float } %inserted.real, float %arg.val.1, 1
  %.15 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 10
  %.16 = bitcast i8* %.15 to { float, float }*
  %.17 = bitcast i8* %.15 to float*
  %.18 = load float, float* %.17, align 1
  %.19 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 14
  %tmp = bitcast i8* %.19 to float*
  %.20 = load float, float* %tmp, align 1
  %inserted.real.1 = insertvalue { float, float } undef, float %.18, 0
  %inserted.imag.1 = insertvalue { float, float } %inserted.real.1, float %.20, 1
  store { float, float } %inserted.imag, { float, float }* %.16, align 1
  store { float, float } %inserted.imag.1, { float, float }* %retptr, align 4
  ret i32 0
}


; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X64

define void @test () {
; X86-LABEL: test:
; X86:       # BB#0:
; X86-NEXT:    movb $0, (%eax)
; X86-NEXT:    retl
;
; X64-LABEL: test:
; X64:       # BB#0:
; X64-NEXT:    movb $0, (%rax)
; X64-NEXT:    retq
  store <2 x i4> zeroinitializer, <2 x i4>* undef, align 1
  ret void
}


; RUN: not llvm-as -disable-output <%s 2>&1 | FileCheck %s
; Check that the debug info verifier gives nice errors for bad type refs
; (rather than crashing).
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"Debug Info Version", i32 3}

; Make a bunch of type references.  Note that !4 references !"0.bad" (instead
; of !"4.bad") to test error ordering.
!typerefs = !{!1, !2, !3, !4}
!1 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"1.good")
!2 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"2.bad")
!3 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"3.good")
!4 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !"0.bad")

; Add a minimal compile unit to resolve some of the type references.
!llvm.dbg.cu = !{!5}
!5 = !MDCompileUnit(file: !6, language: DW_LANG_C99, retainedTypes: !7)
!6 = !MDFile(filename: "file.c", directory: "/path/to/dir")
!7 = !{!8, !9}
!8 = !MDCompositeType(tag: DW_TAG_structure_type, identifier: "1.good")
!9 = !MDCompositeType(tag: DW_TAG_structure_type, identifier: "3.good")

; CHECK:      assembly parsed, but does not verify
; CHECK-NEXT: unresolved type ref
; CHECK-NEXT: !"0.bad"
; CHECK-NEXT: !MDDerivedType(tag: DW_TAG_pointer_type
; CHECK-SAME:                baseType: !"0.bad"
; CHECK-NEXT: unresolved type ref
; CHECK-NEXT: !"2.bad"
; CHECK-NEXT: !MDDerivedType(tag: DW_TAG_pointer_type
; CHECK-SAME:                baseType: !"2.bad"
; CHECK-NOT:  unresolved


Add a testcase showing that scalarrepl supports first class structs.

; This testcase shows that scalarrepl is able to replace struct alloca's which
; are directly loaded from or stored to (using the first class aggregates
; feature).

; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis > %t
; RUN: cat %t | not grep alloca

%struct.foo = type { i32, i32 }

define i32 @test(%struct.foo* %P) {
entry:
	%L = alloca %struct.foo, align 8		; <%struct.foo*> [#uses=2]
        %V = load %struct.foo* %P
        store %struct.foo %V, %struct.foo* %L

	%tmp4 = getelementptr %struct.foo* %L, i32 0, i32 0		; <i32*> [#uses=1]
	%tmp5 = load i32* %tmp4		; <i32> [#uses=1]
	ret i32 %tmp5
}

define %struct.foo @test2(i32 %A, i32 %B) {
entry:
	%L = alloca %struct.foo, align 8		; <%struct.foo*> [#uses=2]
        %L.0 = getelementptr %struct.foo* %L, i32 0, i32 0
        store i32 %A, i32* %L.0
        %L.1 = getelementptr %struct.foo* %L, i32 0, i32 1
        store i32 %B, i32* %L.1
        %V = load %struct.foo* %L
        ret %struct.foo %V
}


Add testcase for r133050 which added support for printing and parsing escaped names for named metadata nodes.

; RUN: llvm-as < %s | llvm-dis | FileCheck %s

!0 = metadata !{metadata !"zero"}
!1 = metadata !{metadata !"one"}
!2 = metadata !{metadata !"two"}

!foo = !{!0, !1, !2}
; CHECK: !foo = !{!0, !1, !2}

!\23pragma = !{!0, !1, !2}
; CHECK: !\23pragma = !{!0, !1, !2}

; \31 is the digit '1'. On emission, we escape the first character (to avoid
; conflicting with anonymous metadata), but not the subsequent ones.
!\31\31\31 = !{!0, !1, !2}
; CHECK: !\3111 = !{!0, !1, !2}

!\22name\22 = !{!0, !1, !2}
; CHECK: !\22name\22 = !{!0, !1, !2}

; \x doesn't mean anything, so we parse it literally but escape the \ into \5C
; when emitting it, followed by xfoo.
!\xfoo = !{!0, !1, !2}
; CHECK: !\5Cxfoo = !{!0, !1, !2}


; RUN: llc -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
define <8 x i16> @test(<4 x i32> %a) {
entry:
  %0 = tail call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %a, <4 x i32> %a)
  ret <8 x i16> %0
}
; CHECK: vpkswss 2,

declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>)


; REQUIRES: asserts
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner 2>&1 \
; RUN:       >/dev/null | FileCheck %s
define dso_local void @sha512() #0 {
;CHECK: prolog:
;CHECK:        %16:g8rc = ADD8 %21:g8rc, %20:g8rc
;CHECK: epilog:
;CHECK:        %23:g8rc_and_g8rc_nox0 = PHI %5:g8rc_and_g8rc_nox0, %bb.3, %18:g8rc_and_g8rc_nox0, %bb.4
;CHECK-NEXT:   %24:g8rc = PHI %6:g8rc, %bb.3, %16:g8rc, %bb.4
;CHECK-NEXT:   %25:g8rc = PHI %6:g8rc, %bb.3, %16:g8rc, %bb.4
  br label %1

1:                                                ; preds = %1, %0
  %2 = phi i64 [ 0, %0 ], [ %12, %1 ]
  %3 = phi i64 [ undef, %0 ], [ %11, %1 ]
  %4 = phi i64 [ undef, %0 ], [ %3, %1 ]
  %5 = getelementptr inbounds [80 x i64], [80 x i64]* null, i64 0, i64 %2
  %6 = load i64, i64* %5, align 8
  %7 = add i64 0, %6
  %8 = and i64 %3, %4
  %9 = or i64 0, %8
  %10 = add i64 0, %9
  %11 = add i64 %10, %7
  %12 = add nuw nsw i64 %2, 1
  %13 = icmp eq i64 %12, 80
  br i1 %13, label %14, label %1

14:                                               ; preds = %1
  %15 = add i64 %4, 0
  store i64 %15, i64* undef, align 8
  ret void
}


; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"

define float @foo(float %x) nounwind readnone ssp {
entry:
; CHECK-NOT: cvtss2sd
; CHECK-NOT: sqrtsd
; CHECK-NOT: cvtsd2ss
; CHECK: sqrtss
  %conv = fpext float %x to double                ; <double> [#uses=1]
  %call = tail call double @sqrt(double %conv) nounwind ; <double> [#uses=1]
  %conv1 = fptrunc double %call to float          ; <float> [#uses=1]
  ret float %conv1
}

declare double @sqrt(double) readnone


Add a testcase for PR8582, which mysteriously fixed itself, in case the problem comes back some day.


Add a testcase to check that debug info is upgraded when compiling LLVM IR through clang.

; REQUIRES: x86-registered-target
; RUN: %clang_cc1 -triple i386-apple-darwin -disable-llvm-optzns -S %s -o - 2>&1 \
; RUN:   | FileCheck %s
; CHECK: invalid global variable ref
; CHECK: warning: ignoring invalid debug info in {{.*}}.ll

@global = common global i32 0, align 4, !dbg !2

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!5, !6}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "adrian", emissionKind: FullDebug, globals: !{!3})
!1 = !DIFile(filename: "broken.c", directory: "/")
!2 = !DIGlobalVariableExpression(var: !3, expr: !DIExpression())
!3 = !DIGlobalVariable(name: "g", scope: !0, file: !1, line: 1, type: !1, isLocal: false, isDefinition: true)
!5 = !{i32 2, !"Dwarf Version", i32 4}
!6 = !{i32 1, !"Debug Info Version", i32 3}


Add a test case to verify that misusing anyregcc crashes as expected.

; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s
;
; Check that misuse of anyregcc results in a compile time error.

; CHECK: LLVM ERROR: ran out of registers during register allocation
define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                        i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                        i64 %v13, i64 %v14, i64 %v15, i64 %v16) {
entry:
  %result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 16,
                i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6,
                i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
                i64 %v13, i64 %v14, i64 %v15, i64 %v16)
  ret i64 %result
}

declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)


; RUN: llvm-as < %s | llc

declare float %llvm.sqrt(float)
declare double %llvm.sqrt(double)

double %test_sqrt(float %F) {
	%G = call float %llvm.sqrt(float %F)
	%H = cast float %G to double
	%I = call double %llvm.sqrt(double %H)
	ret double %I
}


Test case for forward declared global array with no size

; RUN: if as < %s | opt -funcresolve -disable-output 2>&1 | grep WARNING
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi
%__popcount_tab = external constant [0 x ubyte]
%__popcount_tab = constant [4 x ubyte] c"\00\01\01\02"

void %test() {
	getelementptr [0 x ubyte]* %__popcount_tab, long 0, long 2
	getelementptr [4 x ubyte]* %__popcount_tab, long 0, long 2
	ret void
}


; RUN: opt < %s -ipsccp -S | FileCheck %s
; PR36485
; musttail call result can\'t be replaced with a constant, unless the call
; can be removed

declare i32 @external()

define i8* @start(i8 %v) {
  %c1 = icmp eq i8 %v, 0
  br i1 %c1, label %true, label %false
true:
  ; CHECK: %ca = musttail call i8* @side_effects(i8 %v)
  ; CHECK: ret i8* %ca
  %ca = musttail call i8* @side_effects(i8 %v)
  ret i8* %ca
false:
  %c2 = icmp eq i8 %v, 1
  br i1 %c2, label %c2_true, label %c2_false
c2_true:
  ; CHECK: %ca1 = musttail call i8* @no_side_effects(i8 %v)
  ; CHECK: ret i8* %ca1
  %ca1 = musttail call i8* @no_side_effects(i8 %v)
  ret i8* %ca1
c2_false:
  ; CHECK: %ca2 = musttail call i8* @dont_zap_me(i8 %v)
  ; CHECK: ret i8* %ca2
  %ca2 = musttail call i8* @dont_zap_me(i8 %v)
  ret i8* %ca2
}

define internal i8* @side_effects(i8 %v) {
  %i1 = call i32 @external()

  ; since this goes back to `start` the SCPP should be see that the return value
  ; is always `null`.
  ; The call can't be removed due to `external` call above, though.

  ; CHECK: %ca = musttail call i8* @start(i8 %v)
  %ca = musttail call i8* @start(i8 %v)

  ; Thus the result must be returned anyway
  ; CHECK: ret i8* %ca
  ret i8* %ca
}

define internal i8* @no_side_effects(i8 %v) readonly nounwind {
  ; CHECK: ret i8* null
  ret i8* null
}

define internal i8* @dont_zap_me(i8 %v) {
  %i1 = call i32 @external()

  ; The call to this function cannot be removed due to side effects. Thus the
  ; return value should stay as it is, and should not be zapped.
  ; CHECK: ret i8* null
  ret i8* null
}


Add a new testcase for memory corruption issues.

; RUN: llvm-as < %s | opt -gvnpre | llvm-dis

define i32 @TreeCCStreamFlush(i8* %stream) {
entry:
	br i1 false, label %bb55.preheader, label %cond_true

cond_true:		; preds = %entry
	ret i32 0

bb55.preheader:		; preds = %entry
	%tmp57 = icmp eq i8* null, null		; <i1> [#uses=0]
	br i1 false, label %cond_next106, label %bb124

cond_next106:		; preds = %bb55.preheader
	%tmp109 = load i8** null
	br i1 false, label %bb124, label %bb116

bb116:		; preds = %cond_next106
	ret i32 0

bb124:		; preds = %cond_next106, %bb55.preheader
	%buffer.4 = phi i8* [ null, %bb55.preheader ], [ %tmp109, %cond_next106 ]
	%tmp131 = icmp eq i8* %buffer.4, null
	%bothcond = or i1 %tmp131, false
	ret i32 0
}


declare void @pocl.barrier()

; Use noduplicate to avoid unwanted (illegal in OpenCL C semantics)
; code motion / replication of barriers.
define void @barrier(i32 %flags) noduplicate {
entry:
  call void @pocl.barrier()
  ret void
}

Revert "Use noduplicate to avoid unwanted (illegal in OpenCL C semantics)"

declare void @pocl.barrier()

define void @barrier(i32 %flags) {
entry:
  call void @pocl.barrier()
  ret void
}


Test for the the problem with xors being changed into ands when the set bits aren't the same for both args of the xor. This transformation is in the function TargetLowering::SimplifyDemandedBits in the file lib/CodeGen/SelectionDAG/TargetLowering.cpp.

; RUN: llc -mtriple=i386-apple-darwin9 -fast-isel=false -O0 < %s | FileCheck %s

; Gather non-machine specific tests for the transformations in
; CodeGen/SelectionDAG/TargetLowering.  Currently, these
; can't be tested easily by checking the SDNodes that are
; the data structures that these transformations act on.
; Therefore, use X86 assembler output to check against.

; rdar://11195364 A problem with the transformation:
;  If all of the demanded bits on one side are known, and all of the set
;  bits on that side are also known to be set on the other side, turn this
;  into an AND, as we know the bits will be cleared.
; The known set (one) bits for the arguments %xor1 are not the same, so the
; transformation should not occur
define void @foo(i32 %i32In1, i32 %i32In2, i32 %i32In3, i32 %i32In4,
                 i32 %i32In5, i32 %i32In6, i32* %i32StarOut, i1 %i1In1,
                 i32* %i32SelOut) nounwind {
    %and3 = and i32 %i32In1, 1362779777
    %or2 = or i32 %i32In2, %i32In3
    %and2 = and i32 %or2, 1362779777
    %xor3 = xor i32 %and3, %and2
    ; CHECK: shll
    %shl1 = shl i32 %xor3, %i32In4
    %sub1 = sub i32 %or2, %shl1
    %add1 = add i32 %sub1, %i32In5
    %and1 = and i32 %add1, 1
    %xor2 = xor i32 %and1, 1
    %or1 = or i32 %xor2, 364806994 ;0x15BE8352
    ; CHECK-NOT: andl $96239955
    %xor1 = xor i32 %or1, 268567040 ;0x10020200
    ; force an output so not DCE'd
    store i32 %xor1, i32* %i32StarOut
    ; force not fast isel by using a select
    %i32SelVal = select i1 %i1In1, i32 %i32In1, i32 %xor1
    store i32 %i32SelVal, i32* %i32SelOut
    ; CHECK: ret
    ret void
}


; RUN: llvm-as %s -o %t.o
; RUN: %gold -shared -m elf_x86_64 -o %t2 -plugin %llvmshlibdir/LLVMgold.so %t.o
; RUN: nm %t2 | FileCheck %s
; CHECK: PrepareAndDispatch

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

module asm "call PrepareAndDispatch@plt"
module asm "\09"


Add a test case for PR697, ensuring the linker works with ConstantPacked.

; RUN: llvm-as %s -f -o %s.bc ; llvm-link -f -o %s.linked %s.bc

target endian = big
target pointersize = 32
target triple = "powerpc-apple-darwin7.7.0"
deplibs = [ "c", "crtend" ]
%source = global <4 x int> < int 0, int 1, int 2, int 3 >

implementation   ; Functions:

int %main() {
entry:
        ret int 0
}


Add a test case for left shift by 1. We should not be using lea for this.

; RUN: llvm-as < %s | llc -march=x86 | not grep 'leal'

%x = external global int

int %test() {
	%tmp.0 = load int* %x
	%tmp.1 = shl int %tmp.0, ubyte 1
	ret int %tmp.1
}


; RUN: llvm-as < %s | llc -march=x86 -optimize-ext-uses=true | grep movw | count 1

define i16 @t() signext  {
entry:
        %tmp180 = load i16* null, align 2               ; <i16> [#uses=3]
        %tmp180181 = sext i16 %tmp180 to i32            ; <i32> [#uses=1]
        %tmp182 = add i16 %tmp180, 10
        %tmp185 = icmp slt i16 %tmp182, 0               ; <i1> [#uses=1]
        br i1 %tmp185, label %cond_true188, label %cond_next245

cond_true188:           ; preds = %entry
        %tmp195196 = trunc i16 %tmp180 to i8            ; <i8> [#uses=0]
        ret i16 %tmp180

cond_next245:           ; preds = %entry
        %tmp256 = and i32 %tmp180181, 15                ; <i32> [#uses=0]
        %tmp3 = trunc i32 %tmp256 to i16
        ret i16 %tmp3
}


; Test that appending linkage works correctly when arrays are the same size.

; RUN: echo "%X = appending global [1x int] [int 8]" | as > Output/%s.2.bc
; RUN: as < %s > Output/%s.1.bc
; RUN: link Output/%s.[12].bc | dis | grep 7 | grep 8

%X = appending global [1 x int] [int 7]


; RUN: opt %s -tailcallelim -pass-remarks=tailcallelim -o /dev/null 2>&1 | FileCheck %s
; RUN: opt %s -o /dev/null -passes='require<opt-remark-emit>,tailcallelim' -pass-remarks=tailcallelim 2>&1 | FileCheck %s

; CHECK: /home/davide/pat.c:2:20: marked as tail call candidate
; CHECK: /home/davide/pat.c:2:20: transforming tail recursion into loop
define i32 @fib(i32 %n) nounwind ssp {
entry:
  %cmp = icmp slt i32 %n, 2
  br i1 %cmp, label %if.then, label %if.end

if.then:                                          ; preds = %entry
  br label %return

if.end:                                           ; preds = %entry
  %sub = add nsw i32 %n, -2
  %call = call i32 @fib(i32 %sub)
  %sub3 = add nsw i32 %n, -1
  %call4 = call i32 @fib(i32 %sub3), !dbg !8
  %add = add nsw i32 %call, %call4
  br label %return

return:                                           ; preds = %if.end, %if.then
  %retval.0 = phi i32 [ 1, %if.then ], [ %add, %if.end ]
  ret i32 %retval.0
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!llvm.ident = !{!5}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2)
!1 = !DIFile(filename: "/home/davide/pat.c", directory: "/tmp")
!2 = !{}
!3 = !{i32 2, !"Debug Info Version", i32 3}
!4 = !{i32 1, !"PIC Level", i32 2}
!5 = !{!"clang version 3.9.0 "}
!6 = distinct !DISubprogram(name: "success", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !2)
!7 = !DISubroutineType(types: !2)
!8 = !DILocation(line: 2, column: 20, scope: !6)


; RUN: opt -S -indvars  < %s | FileCheck %s
; REQUIRES: asserts
; XFAIL: *

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"

define void @test() {
; CHECK-LABEL: @test

bb:
  br label %bb2

bb1:                                              ; No predecessors!
  br label %bb2

bb2:                                              ; preds = %bb1, %bb
  %tmp = phi i32 [ -9, %bb ], [ %tmp6, %bb1 ]
  br label %bb3

bb3:                                              ; preds = %bb10, %bb2
  %tmp4 = phi i32 [ -9, %bb2 ], [ %tmp6, %bb10 ]
  br i1 undef, label %bb5, label %bb12

bb5:                                              ; preds = %bb3
  %tmp6 = add i32 %tmp4, -1
  %tmp7 = zext i32 %tmp6 to i64
  br i1 undef, label %bb8, label %bb9

bb8:                                              ; preds = %bb5
  br label %bb10

bb9:                                              ; preds = %bb5
  br label %bb10

bb10:                                             ; preds = %bb9, %bb8
  %tmp11 = and i64 undef, %tmp7
  br label %bb3

bb12:                                             ; preds = %bb3
  ret void
}


Add test showing missing compute known bits PSADBW handling

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64

; Only bottom 16 bits are set - upper 48 bits are zero.
define <2 x i64> @combine_psadbw_shift(<16 x i8> %0, <16 x i8> %1) {
; CHECK-LABEL: combine_psadbw_shift:
; CHECK:       # %bb.0:
; CHECK-NEXT:    psadbw %xmm1, %xmm0
; CHECK-NEXT:    psrlq $48, %xmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
  %4 = lshr <2 x i64> %3, <i64 48, i64 48>
  ret <2 x i64> %4
}

declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)


Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets

; Check that eh_return & unwind_init were properly lowered
; RUN: llvm-as < %s | llc | grep %ebp | count 9
; RUN: llvm-as < %s | llc | grep %ecx | count 5

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i386-pc-linux"

define i8* @test(i32 %a, i8* %b)  {
entry:
  call void @llvm.eh.unwind.init()
  %foo   = alloca i32
  call void @llvm.eh.return.i32(i32 %a, i8* %b)
  unreachable
}

declare void @llvm.eh.return.i32(i32, i8*)
declare void @llvm.eh.unwind.init()


Add a testcase for optimizing the strcpy libcall.

; Test that the StrCatOptimizer works correctly
; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | not grep 'call.*strcat'

declare sbyte* %strcpy(sbyte*,sbyte*)
declare int %puts(sbyte*)
%hello = constant [6 x sbyte] c"hello\00"
%null = constant [1 x sbyte] c"\00"
%null_hello = constant [7 x sbyte] c"\00hello\00"

implementation   ; Functions:

int %main () {
  %target = alloca [1024 x sbyte]
  %arg1 = getelementptr [1024 x sbyte]* %target, int 0, int 0
  store sbyte 0, sbyte* %arg1
  %arg2 = getelementptr [6 x sbyte]* %hello, int 0, int 0
  %rslt1 = call sbyte* %strcpy(sbyte* %arg1, sbyte* %arg2)
  %arg3 = getelementptr [1 x sbyte]* %null, int 0, int 0
  %rslt2 = call sbyte* %strcpy(sbyte* %rslt1, sbyte* %arg3)
  %arg4 = getelementptr [7 x sbyte]* %null_hello, int 0, int 0
  %rslt3 = call sbyte* %strcpy(sbyte* %rslt2, sbyte* %arg4)
  call int %puts(sbyte* %rslt3)
  ret int 0
}


Check in an old test that never made it into CVS

; RUN: echo "%G = weak global {{{{double}}}} zeroinitializer" | llvm-as > %t.out2.bc
; RUN: llvm-as < %s > %t.out1.bc
; RUN: llvm-link %t.out[12].bc | llvm-dis | not grep '\}'

; When linked, the global above should be eliminated, being merged with the
; global below.

%G = global double 1.0


; RUN: llvm-as < %s | llvm-dis | FileCheck %s

define void @test1() forcesizeopt {
; CHECK: define void @test1() forcesizeopt
        ret void
}


Add a test case for SSE fcopysign using SSE bitwise operations.

; RUN: llvm-as | llc -march=x86 -mattr=+sse2 &&
; RUN: llvm-as | llc -march=x86 -mattr=+sse2 | grep pslldq | wc -l | grep 1 &&
; RUN: llvm-as | llc -march=x86 -mattr=+sse2 | not getp test

define float %test1(float %a, float %b) {
	%tmp = tail call float %copysignf( float %b, float %a )
	ret float %tmp
}

define double %test2(double %a, float %b, float %c) {
	%tmp1 = add float %b, %c
	%tmp2 = fpext float %tmp1 to double
	%tmp = tail call double %copysign( double %a, double %tmp2 )
	ret double %tmp
}

declare float %copysignf(float, float)
declare double %copysign(double, double)


; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsb	 | count 2

%struct.s = type { i8, i8, i8, i8, i8, i8 }

define void @g(i8 signext  %a1, i8 signext  %a2, i8 signext  %a3,
	 i8 signext  %a4, i8 signext  %a5, i8 signext  %a6) {
entry:
        %a = alloca %struct.s
        %tmp = getelementptr %struct.s* %a, i32 0, i32 0
        store i8 %a1, i8* %tmp, align 8
        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
        store i8 %a2, i8* %tmp2, align 8
        %tmp4 = getelementptr %struct.s* %a, i32 0, i32 2
        store i8 %a3, i8* %tmp4, align 8
        %tmp6 = getelementptr %struct.s* %a, i32 0, i32 3
        store i8 %a4, i8* %tmp6, align 8
        %tmp8 = getelementptr %struct.s* %a, i32 0, i32 4
        store i8 %a5, i8* %tmp8, align 8
        %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5
        store i8 %a6, i8* %tmp10, align 8
        call void @f( %struct.s* %a byval )
        call void @f( %struct.s* %a byval )
        ret void
}

declare void @f(%struct.s* byval)


; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
; RUN: llc -mtriple=thumbv7-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP

declare float @llvm.arm.vcvtr.f32(float)
declare float @llvm.arm.vcvtru.f32(float)
declare float @llvm.arm.vcvtr.f64(double)
declare float @llvm.arm.vcvtru.f64(double)

define float @test_vcvtrf0(float %f) {
entry:
; CHECK-VFP:  vcvtr.s32.f32  s0, s0
  %vcvtr = tail call float @llvm.arm.vcvtr.f32(float %f)
  ret float %vcvtr
}

define float @test_vcvtrf1(float %f) {
entry:
; CHECK-VFP:  vcvtr.u32.f32  s0, s0
  %vcvtr = tail call float @llvm.arm.vcvtru.f32(float %f)
  ret float %vcvtr
}

define float @test_vcvtrd0(double %d) {
entry:
; CHECK-VFP: vcvtr.s32.f64  s0, d{{.*}}
  %vcvtr = tail call float @llvm.arm.vcvtr.f64(double %d)
  ret float %vcvtr
}

define float @test_vcvtrd1(double %d) {
entry:
; CHECK-VFP: vcvtr.u32.f64  s0, d{{.*}}
  %vcvtr = tail call float @llvm.arm.vcvtru.f64(double %d)
  ret float %vcvtr
}


Add test case that was supposed to go with r355116.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s

; Make sure this sequence doesn't hang in DAG combine.

define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vandps %ymm2, %ymm0, %ymm0
; CHECK-NEXT:    vandps {{\.LCPI.*}}, %ymm1, %ymm1
; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm2
; CHECK-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
; CHECK-NEXT:    vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT:    retl
  %a = shufflevector <4 x i64> %y, <4 x i64> <i64 12345, i64 67890, i64 13579, i64 24680>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %b = and <8 x i64> %x, %a
  %c = trunc <8 x i64> %b to <8 x i32>
  ret <8 x i32> %c
}


Add an llc testcase analogous to test/LTO/X86/strip-debug-info.ll

; RUN: llvm-as -disable-verify %s -o %t.bc
; ---- Full LTO ---------------------------------------------
; RUN: llc -filetype=asm -o - %t.bc 2>&1 | FileCheck %s
; CHECK-NOT: Broken module found
; CHECK: warning{{.*}} ignoring invalid debug info
; CHECK-NOT: Broken module found
; CHECK: foo
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.12"

declare void @bar()

define void @foo() {
  call void @bar()
  ret void
}

!llvm.module.flags = !{!0}
!llvm.dbg.cu = !{!1}

!0 = !{i32 2, !"Debug Info Version", i32 3}
!1 = !DIFile(filename: "broken", directory: "")


; RUN: llvm-as < %s | llc -mtriple=i686-pc-linux-gnu -mcpu=athlon -relocation-model=pic
; PR1545

@.str97 = external constant [56 x i8]		; <[56 x i8]*> [#uses=1]

declare void @PR_LogPrint(i8*, ...)

define i32 @_ZN13nsPrintEngine19SetupToPrintContentEP16nsIDeviceContextP12nsIDOMWindow() {
entry:
	br i1 false, label %cond_true122, label %cond_next453

cond_true122:		; preds = %entry
	br i1 false, label %bb164, label %cond_true136

cond_true136:		; preds = %cond_true122
	ret i32 0

bb164:		; preds = %cond_true122
	br i1 false, label %bb383, label %cond_true354

cond_true354:		; preds = %bb164
	ret i32 0

bb383:		; preds = %bb164
	%tmp408 = load float* null		; <float> [#uses=2]
	br i1 false, label %cond_true425, label %cond_next443

cond_true425:		; preds = %bb383
	%tmp430 = load float* null		; <float> [#uses=1]
	%tmp432 = sub float %tmp430, %tmp408		; <float> [#uses=1]
	%tmp432433 = fpext float %tmp432 to double		; <double> [#uses=1]
	%tmp434435 = fpext float %tmp408 to double		; <double> [#uses=1]
	call void (i8*, ...)* @PR_LogPrint( i8* getelementptr ([56 x i8]* @.str97, i32 0, i32 0), double 0.000000e+00, double %tmp434435, double %tmp432433 )
	ret i32 0

cond_next443:		; preds = %bb383
	ret i32 0

cond_next453:		; preds = %entry
	ret i32 0
}


Add test case for varint logical right shift with shift distance 64


; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -disable-mmx -o %t -f
; RUN: grep divdi3  %t | count 2

; Test case for r63760 where we generate a legalization assert that an illegal
; type has been inserted by LegalizeDAG after LegalizeType has run. With sse2,
; v2i64 is a legal type but with mmx disabled, i64 is an illegal type. When
; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make
; two 64 bit divide library calls which introduces i64 nodes that needs to be
; promoted.

define <2 x i64> @test_long_div(<2 x i64> %num, <2 x i64> %div) {
  %div.r = sdiv <2 x i64> %num, %div
  ret <2 x i64>  %div.r
}


Add another failing test on LoopSimplifyCFG

; XFAIL: *
; REQUIRES: asserts
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s

target triple = "x86_64-unknown-linux-gnu"

define void @test() {

; CHECK-LABEL: @test(

  br label %bb1

bb1:                                              ; preds = %bb4, %0
  br label %bb2

bb2:                                              ; preds = %bb6, %bb1
  br label %bb3

bb3:                                              ; preds = %bb8, %bb3, %bb2
  br i1 false, label %bb4, label %bb3

bb4:                                              ; preds = %bb8, %bb3
  br i1 undef, label %bb1, label %bb6

bb6:                                              ; preds = %bb4
  br i1 undef, label %bb2, label %bb8

bb8:                                              ; preds = %bb6
  br i1 true, label %bb4, label %bb3
}


Add a testcase for load short -> uint, which is currently emitted as a zextload + sign_extend_inreg rather than a sextload.

; RUN: llvm-as < %s | llc -march=ppc32 | grep lha
; XFAIL: *

uint %test(short* %a) {
entry:
    %tmp.1 = load short* %a
    %tmp.2 = cast short %tmp.1 to uint
    ret uint %tmp.2
}


Add a testcase cee should eventually pass

; a load or store of a pointer indicates that the pointer is not null.
; Any succeeding uses of the pointer should get this info

; RUN: if as < %s | opt -cee -instcombine -simplifycfg | dis | grep br
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

implementation   ; Functions:

int %nullptr(int* %j) {
bb0:
	store int 7, int* %j               ; j != null
	%cond220 = seteq int* %j, null     ; F
	br bool %cond220, label %bb3, label %bb4  ; direct branch

bb3:
	ret int 4                          ; Dead code
bb4:
	ret int 3                          ; Live code
}


Add a testcase for the problem fixed in r65289.

; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {align 32} | count 1

; It's tempting to have an instcombine in which the src pointer of a
; memcpy is aligned up to the alignment of the destination, however
; there are pitfalls. If the src is an alloca, aligning it beyond what
; the target's stack pointer is aligned at will require dynamic
; stack realignment, which can require functions that don't otherwise
; need a frame pointer to need one.
;
; Abstaining from this transform is not the only way to approach this
; issue. Some late phase could be smart enough to reduce alloca
; alignments when they are greater than they need to be. Or, codegen
; could do dynamic alignment for just the one alloca, and leave the
; main stack pointer at its standard alignment.

@dst = global [1024 x i8] zeroinitializer, align 32

define void @foo() nounwind {
entry:
	%src = alloca [1024 x i8], align 1
	%src1 = getelementptr [1024 x i8]* %src, i32 0, i32 0
	call void @llvm.memcpy.i32(i8* getelementptr ([1024 x i8]* @dst, i32 0, i32 0), i8* %src1, i32 1024, i32 1)
	call void @frob(i8* %src1) nounwind
	ret void
}

declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind

declare void @frob(i8*)


; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64

define i32 @pr32690(i32) {
; X86-LABEL: pr32690:
; X86:       # %bb.0:
; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT:    xorl %eax, %eax
; X86-NEXT:    addl $63, %ecx
; X86-NEXT:    setb %al
; X86-NEXT:    shldl $26, %ecx, %eax
; X86-NEXT:    retl
;
; X64-LABEL: pr32690:
; X64:       # %bb.0:
; X64-NEXT:    movl %edi, %eax
; X64-NEXT:    addq $63, %rax
; X64-NEXT:    shrq $6, %rax
; X64-NEXT:    # kill: def %eax killed %eax killed %rax
; X64-NEXT:    retq
  %2 = zext i32 %0 to i64
  %3 = add nuw nsw i64 %2, 63
  %4 = lshr i64 %3, 6
  %5 = trunc i64 %4 to i32
  ret i32 %5
}


Test case for PR1082, an llvm-upgrade bug.

; RUN: llvm-upgrade < %s | llvm-as -o /dev/null -f

implementation   ; Functions:

void %interpret() {
entry:
        %x = bitcast sbyte  1 to sbyte
        %x = bitcast ubyte  1 to ubyte
        %x = bitcast short  1 to short
        %x = bitcast ushort 1 to ushort
        %x = bitcast int    1 to int
        %x = bitcast uint   1 to uint
        %x = bitcast ulong  1 to ulong
        %x = inttoptr ulong %x to sbyte*
        %tmp = inttoptr ulong %x to float*
        %tmp7360 = bitcast ubyte %x to sbyte
        %tmp7361 = sub ubyte 0, %tmp7360
        br label %next

next:		; preds = %cond_false165, %cond_true163
	%index.0 = phi uint [ undef, %entry ], [ %index.0, %next ]
        br label %next
}


Add test case that was supposed to go with r360102.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s

define i64 @test1() nounwind {
; CHECK-LABEL: test1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    #APP
; CHECK-NEXT:    vmovq {{.*#+}} xmm16 = mem[0],zero
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    vmovq %xmm16, %rax
; CHECK-NEXT:    retq
entry:
  %0 = tail call i64 asm sideeffect "vmovq $1, $0", "={xmm16},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind
  ret i64 %0
}