Add a testcase demoing some of ScalarEvolution's new trip count logic.

; RUN: llvm-as < %s | opt -analyze -disable-output -scalar-evolution \
; RUN:  | grep {max backedge-taken count is 1\$}

@mode_table = global [4 x i32] zeroinitializer          ; <[4 x i32]*> [#uses=1]

define i8 @f() {
entry:
  tail call i32 @fegetround( )          ; <i32>:0 [#uses=1]
  br label %bb

bb:             ; preds = %bb4, %entry
  %mode.0 = phi i8 [ 0, %entry ], [ %indvar.next, %bb4 ]                ; <i8> [#uses=4]
  zext i8 %mode.0 to i32                ; <i32>:1 [#uses=1]
  getelementptr [4 x i32]* @mode_table, i32 0, i32 %1           ; <i32*>:2 [#uses=1]
  load i32* %2, align 4         ; <i32>:3 [#uses=1]
  icmp eq i32 %3, %0            ; <i1>:4 [#uses=1]
  br i1 %4, label %bb1, label %bb2

bb1:            ; preds = %bb
  ret i8 %mode.0

bb2:            ; preds = %bb
  icmp eq i8 %mode.0, 1         ; <i1>:5 [#uses=1]
  br i1 %5, label %bb5, label %bb4

bb4:            ; preds = %bb2
  %indvar.next = add i8 %mode.0, 1              ; <i8> [#uses=1]
  br label %bb

bb5:            ; preds = %bb2
  tail call void @raise_exception( ) noreturn
  unreachable
}

declare i32 @fegetround()

declare void @raise_exception() noreturn


Test case for PR1271 involving construction of a bad mask to replace a shift instruction.

; PR1271
; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep 'br i1 %1'
%struct..0anon = type { i32, i32 }
%struct..1anon = type { double }

define i32 @main() {
entry:
	%u = alloca %struct..1anon, align 8		; <%struct..1anon*> [#uses=4]
	%tmp1 = getelementptr %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
	store double 0x7FF0000000000000, double* %tmp1
	%tmp3 = getelementptr %struct..1anon* %u, i32 0, i32 0		; <double*> [#uses=1]
	%tmp34 = bitcast double* %tmp3 to %struct..0anon*		; <%struct..0anon*> [#uses=1]
	%tmp5 = getelementptr %struct..0anon* %tmp34, i32 0, i32 1		; <i32*> [#uses=1]
	%tmp6 = load i32* %tmp5		; <i32> [#uses=1]
	%tmp7 = shl i32 %tmp6, 1		; <i32> [#uses=1]
	%tmp8 = lshr i32 %tmp7, 21		; <i32> [#uses=1]
	%tmp89 = trunc i32 %tmp8 to i16		; <i16> [#uses=1]
	icmp ne i16 %tmp89, 2047		; <i1>:0 [#uses=1]
	zext i1 %0 to i8		; <i8>:1 [#uses=1]
	icmp ne i8 %1, 0		; <i1>:2 [#uses=1]
	br i1 %2, label %cond_true, label %cond_false

cond_true:		; preds = %entry
	ret i32 0

cond_false:		; preds = %entry
        ret i32 1
}


; RUN: llc < %s -mcpu=atom | FileCheck %s

; ModuleID = 'bugpoint-reduced-simplified.bc'
target triple = "x86_64-apple-darwin12.5.0"

define i32 @DoLayout() {
entry:
  %tmp1 = load i16* undef, align 2
  %tmp17 = load i16* null, align 2
  %tmp19 = load i16* undef, align 2
  %shl = shl i16 %tmp19, 1
  %add55 = add i16 %tmp17, %tmp1
  %add57 = add i16 %add55, %shl
  %conv60 = zext i16 %add57 to i32
  %add61 = add nsw i32 %conv60, 0
  %conv63 = and i32 %add61, 65535
  ret i32 %conv63
; CHECK: addw
}


Add test for store merge with noimplicitfloat

; RUN: llc -o - %s | FileCheck %s

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios10.0.0"

; PR33475 - Expect 64-bit operations as 128-operations are not legal

; CHECK-LABEL: pr33475
; CHECK-DAG: ldr [[R0:x[0-9]+]], [x1]
; CHECK-DAG: str [[R0]], [x0]
; CHECK-DAG: ldr [[R1:x[0-9]+]], [x1, #8]
; CHECK-DAG: str [[R1]], [x0, #8]
; CHECK-DAG: ldr [[R2:x[0-9]+]], [x1, #16]
; CHECK-DAG: str [[R2]], [x0, #16]
; CHECK-DAG: ldr [[R3:x[0-9]+]], [x1, #24]
; CHECK-DAG: str [[R3]], [x0, #24]

define void @pr33475(i8* %p0, i8* %p1) noimplicitfloat {
    call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p0, i8* %p1, i64 32, i32 4, i1 false)
    ret void
}

declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)


Add a test case to test parameter attributes feature.

; RUN: llvm-as < %s | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN: diff %t1.ll %t2.ll

%FunTy = type i32(i8 @zext)

declare i16 @(sext) "test"(i16 @sext %arg)      ; Differ only by vararg
declare i16 "test2" (i16 %a1, i16 %a2)

implementation

define i32 %main(i32 %argc, i8 **%argv) {
    %val = trunc i32 %argc to i16
    %res = call i16 @sext (i16 @sext) *%test(i16 %val)
    %two = add i16 %res, %res
    %retVal = sext i16 %two to i32
    ret i32 %retVal
}


; RUN: opt < %s -loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -S | FileCheck --enable-var-scope %s

; Make sure we attach memcheck metadata to scalarized memory operations even if
; we're only unrolling.

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"

; CHECK-LABEL: vector.memcheck:
; CHECK-LABEL: vector.body:
; CHECK: load i32, {{.*}} !alias.scope ![[$MD1:[0-9]+]]
; CHECK-LABEL: middle.block:
; CHECK-DAG: ![[$MD1]] = !{![[MD2:[0-9]+]]}
; CHECK-DAG: ![[MD2]] = distinct !{![[MD2]], ![[MD3:[0-9]+]]}
; CHECK-DAG: ![[MD3]] = distinct !{![[MD3]], !"LVerDomain"}

; Function Attrs: norecurse nounwind uwtable
define void @test(i32* nocapture readonly %a, i32* nocapture %b) local_unnamed_addr #0 {
entry:
  br label %for.body

for.body:                                         ; preds = %for.body, %entry
  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
  %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
  %0 = load i32, i32* %arrayidx, align 4
  %add = add nsw i32 %0, 77
  %arrayidx2 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
  store i32 %add, i32* %arrayidx2, align 4
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond = icmp eq i64 %indvars.iv.next, 10000
  br i1 %exitcond, label %for.end, label %for.body

for.end:                                          ; preds = %for.body
  ret void
}

attributes #0 = { norecurse nounwind uwtable }


Add a missing test for the 128-bit local addr space option

; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=SI,GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=CIVI,GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 < %s | FileCheck -check-prefixes=CIVI,GCN %s

; Test if ds_read/write_b128 doesn't gets generated when the option is
; disabled.
; GCN-LABEL: {{^}}local_v4f32_to_2b64
;
; SI-NOT: ds_read_b128
; SI-NOT: ds_write_b128
;
; CIVI: ds_read2_b64
; CIVI: ds_write2_b64
define amdgpu_kernel void @local_v4f32_to_2b64(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) {
  %ld = load <4 x float>, <4 x float> addrspace(3)* %in, align 16
  store <4 x float> %ld, <4 x float> addrspace(3)* %out, align 16
  ret void
}

attributes #0 = { nounwind }


Add a test for r242281 from an old patch of mine.

; RUN: opt < %s -globalsmodref-aa -gvn -S | FileCheck %s

@X = internal global i32 4

define i32 @test_cmpxchg(i32* %P) {
; CHECK-LABEL: @test_cmpxchg
; CHECK-NEXT: store i32 12, i32* @X
; CHECK-NEXT: call void @modrefX_cmpxchg()
; CHECK-NEXT: %V = load i32, i32* @X
; CHECK-NEXT: ret i32 %V
  store i32 12, i32* @X
  call void @modrefX_cmpxchg()
  %V = load i32, i32* @X
  ret i32 %V
}

define void @modrefX_cmpxchg() {
  %1 = cmpxchg i32* @X, i32 0, i32 -1 monotonic monotonic
  ret void
}

define i32 @test_atomicrmw(i32* %P) {
; CHECK-LABEL: @test_atomicrmw
; CHECK-NEXT: store i32 12, i32* @X
; CHECK-NEXT: call void @modrefXatomicrmw()
; CHECK-NEXT: %V = load i32, i32* @X
; CHECK-NEXT: ret i32 %V
  store i32 12, i32* @X
  call void @modrefXatomicrmw()
  %V = load i32, i32* @X
  ret i32 %V
}

define void @modrefXatomicrmw() {
  %1 = atomicrmw add i32* @X, i32 1 acquire
  ret void
}


Add removed inline-assembly-comment test from r277146

; RUN: llc %s -o - | sed -n -e '/@APP/,/@NO_APP/p' > %t
; RUN: sed -n -e 's/^;CHECK://p' %s > %t2
; RUN: diff %t %t2

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "arm-eabi"

; Function Attrs: nounwind uwtable
define void @foo() #0 {
entry:
  call void asm sideeffect "#isolated preprocessor comment", "~{dirflag},~{fpsr},~{flags}"() #0
;CHECK:	@APP
;CHECK:	@isolated preprocessor comment
;CHECK:	@NO_APP
  ret void
}

attributes #0 = { nounwind }

!llvm.ident = !{!0}

!0 = !{!""}


; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs
; Just shouldn't crash, PR28348

%C = type { i8* }

define void @repro(%C* %this, i32 %a) {
  %a_align1 = and i32 %a, -4096
  %a_and = and i32 %a, 4095
  %a_align2 = or i32 %a_and, 4096

  call void @use(i32 %a_align1)

  %C_field = getelementptr inbounds %C, %C* %this, i32 0, i32 0
  %addptr = getelementptr inbounds i8, i8* null, i32 %a_align2
  store i8* %addptr, i8** %C_field, align 4

  ret void
}

declare void @use(i32)


; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {ashr}
; PR1499

define void @av_cmp_q_cond_true(i32* %retval, i32* %tmp9, i64* %tmp10) {
newFuncRoot:
	br label %cond_true

return.exitStub:		; preds = %cond_true
	ret void

cond_true:		; preds = %newFuncRoot
	%tmp30 = load i64* %tmp10		; <i64> [#uses=1]
	%.cast = zext i32 63 to i64		; <i64> [#uses=1]
	%tmp31 = ashr i64 %tmp30, %.cast		; <i64> [#uses=1]
	%tmp3132 = trunc i64 %tmp31 to i32		; <i32> [#uses=1]
	%tmp33 = or i32 %tmp3132, 1		; <i32> [#uses=1]
	store i32 %tmp33, i32* %tmp9
	%tmp34 = load i32* %tmp9		; <i32> [#uses=1]
	store i32 %tmp34, i32* %retval
	br label %return.exitStub
}


Add tests for the NVPTXLowerAggrCopies pass.

; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s

; Verify that the NVPTXLowerAggrCopies pass works as expected - calls to
; llvm.mem* intrinsics get lowered to loops.

declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1

define i8* @memcpy_caller(i8* %dst, i8* %src, i64 %n) #0 {
entry:
  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %n, i32 1, i1 false)
  ret i8* %dst
; CHECK-LABEL: .visible .func (.param .b32 func_retval0) memcpy_caller
; CHECK: LBB[[LABEL:[_0-9]+]]:
; CHECK:      ld.u8 %rs[[REG:[0-9]+]]
; CHECK:      st.u8 [%r{{[0-9]+}}], %rs[[REG]]
; CHECK:      add.s64 %rd[[COUNTER:[0-9]+]], %rd[[COUNTER]], 1
; CHECK-NEXT: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
; CHECK-NEXT: @%p[[PRED]] bra LBB[[LABEL]]
}

define i8* @memset_caller(i8* %dst, i32 %c, i64 %n) #0 {
entry:
  %0 = trunc i32 %c to i8
  tail call void @llvm.memset.p0i8.i64(i8* %dst, i8 %0, i64 %n, i32 1, i1 false)
  ret i8* %dst
; CHECK-LABEL: .visible .func (.param .b32 func_retval0) memset_caller(
; CHECK:      ld.param.u8 %rs[[REG:[0-9]+]]
; CHECK:      LBB[[LABEL:[_0-9]+]]:
; CHECK:      st.u8 [%r{{[0-9]+}}], %rs[[REG]]
; CHECK:      add.s64 %rd[[COUNTER:[0-9]+]], %rd[[COUNTER]], 1
; CHECK-NEXT: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
; CHECK-NEXT: @%p[[PRED]] bra LBB[[LABEL]]
}


Add test case showing incorrect SelectionDAG::ComputeNumSignBits BUILD_VECTOR handling

; RUN: llc < %s -mtriple=aarch64-unknown | FileCheck %s

; PR32273

define void @signbits_vXi1(<4 x i16> %a1) {
; CHECK-LABEL: signbits_vXi1
; CHECK: cmgt v0.4h, v1.4h, v0.4h
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: and w3, w9, #0x1
; CHECK-NEXT: mov w1, wzr
; CHECK-NEXT: mov w2, wzr
; CHECK-NEXT: b foo
  %tmp3 = shufflevector <4 x i16> %a1, <4 x i16> undef, <4 x i32> zeroinitializer
  %tmp5 = add <4 x i16> %tmp3, <i16 18249, i16 6701, i16 -18744, i16 -25086>
  %tmp6 = icmp slt <4 x i16> %tmp5, <i16 1, i16 1, i16 1, i16 1>
  %tmp7 = and <4 x i1> %tmp6, <i1 true, i1 false, i1 false, i1 true>
  %tmp8 = sext <4 x i1> %tmp7 to <4 x i16>
  %tmp9 = extractelement <4 x i16> %tmp8, i32 0
  %tmp10 = zext i16 %tmp9 to i32
  %tmp11 = extractelement <4 x i16> %tmp8, i32 1
  %tmp12 = zext i16 %tmp11 to i32
  %tmp13 = extractelement <4 x i16> %tmp8, i32 2
  %tmp14 = zext i16 %tmp13 to i32
  %tmp15 = extractelement <4 x i16> %tmp8, i32 3
  %tmp16 = zext i16 %tmp15 to i32
  tail call void @foo(i32 %tmp10, i32 %tmp12, i32 %tmp14, i32 %tmp16)
  ret void
}

declare void @foo(i32, i32, i32, i32)


Add testcase to make sure we don't generate a compact unwind section for ELF binaries.

; RUN: llc < %s -mtriple x86_64-apple-macosx10.8.0 -disable-cfi | FileCheck -check-prefix=MACHO %s
; RUN: llc < %s -mtriple x86_64-unknown-linux -disable-cfi | FileCheck -check-prefix=ELF %s

; Make sure we don't generate a compact unwind for ELF.

; MACHO-LABEL: _Z3barv:
; MACHO:       __compact_unwind

; ELF-LABEL:   _Z3barv:
; ELF-NOT:     __compact_unwind

@_ZTIi = external constant i8*

define void @_Z3barv() uwtable {
entry:
  invoke void @_Z3foov()
          to label %try.cont unwind label %lpad

lpad:                                             ; preds = %entry
  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
          catch i8* bitcast (i8** @_ZTIi to i8*)
  %1 = extractvalue { i8*, i32 } %0, 1
  %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*))
  %matches = icmp eq i32 %1, %2
  br i1 %matches, label %catch, label %eh.resume

catch:                                            ; preds = %lpad
  %3 = extractvalue { i8*, i32 } %0, 0
  %4 = tail call i8* @__cxa_begin_catch(i8* %3)
  tail call void @__cxa_end_catch()
  br label %try.cont

try.cont:                                         ; preds = %entry, %catch
  ret void

eh.resume:                                        ; preds = %lpad
  resume { i8*, i32 } %0
}

declare void @_Z3foov()

declare i32 @__gxx_personality_v0(...)

declare i32 @llvm.eh.typeid.for(i8*)

declare i8* @__cxa_begin_catch(i8*)

declare void @__cxa_end_catch()


Add a test case for testing ffs libcall conversion to constant

; Test that the ToAsciiOptimizer works correctly
; RUN: llvm-as < %s | opt -simplify-libcalls | llvm-dis | not grep 'call.*%ffs'

declare int %ffs(int)
declare int %ffsl(int)
declare int %ffsll(long)

implementation   ; Functions:

int %main () {
  %val1 = call int %ffs(int 1)
  %val2 = call int %ffs(int 2048)
  %val3 = call int %ffsl(int 65536)
  %val4 = call int %ffsll(long 1024)
  %val5 = call int %ffsll(long 17179869184)
  %val6 = call int %ffsll(long 1152921504606846976)
  %rslt1 = add int %val1, %val2
  %rslt2 = add int %val3, %val4
  %rslt3 = add int %val5, %val6
  %rslt4 = add int %rslt1, %rslt2
  %rslt5 = add int %rslt4, %rslt3
  ret int %rslt5
}


Add test case that should have been added in r195456.

; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
; RUN: llc -march=mipsel < %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s

; This test originally failed for MSA with a "Cannot select ..." error.
; This was because undef's are ignored when checking if a vector constant is a
; splat, but are legalized to zero if left in the DAG which changes the constant
; into a non-splat.
;
; It should at least successfully build.

define void @autogen_SD2090927243() {
BB:
  br label %CF77

CF77:                                             ; preds = %CF77, %CF80
  %Shuff27 = shufflevector <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>,
                           <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>,
                           <16 x i32> <i32 27, i32 29, i32 31, i32 1, i32 3, i32 5, i32 undef, i32 9, i32 11, i32 13, i32 undef, i32 17, i32 19, i32 21, i32 23, i32 undef>
  %ZE30 = zext <16 x i8> %Shuff27 to <16 x i32>
  %Cmp32 = fcmp ueq float undef, 0x3CDA6E5E40000000
  br i1 %Cmp32, label %CF77, label %CF

CF:                                               ; preds = %CF, %CF81
  %E48 = extractelement <16 x i32> %ZE30, i32 14
  br i1 undef, label %CF, label %CF78

CF78:                                             ; preds = %CF
  ret void
}


Test that MachineSink won't sink across llvm.cuda.syncthreads.

; RUN: llc < %s | FileCheck %s
target triple = "nvptx64-nvidia-cuda"

declare void @llvm.cuda.syncthreads()

; Load a value, then syncthreads.  Branch, and use the loaded value only on one
; side of the branch.  The load shouldn't be sunk beneath the call, because
; syncthreads is modeled as maystore.
define i32 @f(i32 %x, i32* %ptr, i1 %cond) {
Start:
  ; CHECK: ld.u32
  %ptr_val = load i32, i32* %ptr
  ; CHECK: bar.sync
  call void @llvm.cuda.syncthreads()
  br i1 %cond, label %L1, label %L2
L1:
  %ptr_val2 = add i32 %ptr_val, 100
  br label %L2
L2:
  %v4 = phi i32 [ %x, %Start ], [ %ptr_val2, %L1 ]
  %v5 = add i32 %v4, 1000
  ret i32 %v5
}


Add a test to the previous added clo instruction. Patch by Akira again

; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s

; CHECK: clz $2, $4
define i32 @t1(i32 %X) nounwind readnone {
entry:
  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X)
  ret i32 %tmp1
}

declare i32 @llvm.ctlz.i32(i32) nounwind readnone

; CHECK: clz $2, $4
define i32 @t2(i32 %X) nounwind readnone {
entry:
  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X)
  ret i32 %tmp1
}

; CHECK: clo $2, $4
define i32 @t3(i32 %X) nounwind readnone {
entry:
  %neg = xor i32 %X, -1
  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg)
  ret i32 %tmp1
}

; CHECK: clo $2, $4
define i32 @t4(i32 %X) nounwind readnone {
entry:
  %neg = xor i32 %X, -1
  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg)
  ret i32 %tmp1
}


Simplify cfg now eliminates all of the branches in this testcase

; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br

int %test(bool %C, int %V1, int %V2) {
entry:
        br bool %C, label %then, label %Cont

then:
        %V3 = or int %V2, %V1
        br label %Cont
Cont:
	%V4 = phi int [%V1, %entry], [%V3, %then]
	call int %test(bool false, int 0, int 0)           ;; don't fold into preds
        ret int %V1
}


Add a regression test for the load store optimizer.

; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s

; This file contains tests for the AArch64 load/store optimizer.

%struct.A = type { %struct.B, %struct.C }
%struct.B = type { i8*, i8*, i8*, i8* }
%struct.C = type { i32, i32 }

; Check the following transform:
;
; ldr w1, [x0, #32]
;  ...
; add x0, x0, #32
;  ->
; ldr w1, [x0, #32]!

define void @foo(%struct.A* %ptr) nounwind {
; CHECK-LABEL: foo
; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, #32]!
entry:
  %a = getelementptr inbounds %struct.A* %ptr, i64 0, i32 1, i32 0
  %add = load i32* %a, align 4
  br label %bar
bar:
  %c = getelementptr inbounds %struct.A* %ptr, i64 0, i32 1
  tail call void @bar(%struct.C* %c, i32 %add)
  ret void
}

declare void @bar(%struct.C*, i32)


Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications).

; RUN: opt < %s -ipsccp -S | FileCheck %s

; This transformation is safe for atomic loads and stores; check that it works.

@G = internal global i32 17
@C = internal constant i32 222

define i32 @test1() {
	%V = load atomic i32* @G seq_cst, align 4
	%C = icmp eq i32 %V, 17
	br i1 %C, label %T, label %F
T:
	store atomic i32 17, i32* @G seq_cst, align 4
	ret i32 %V
F:
	store atomic i32 123, i32* @G seq_cst, align 4
	ret i32 0
}
; CHECK: define i32 @test1
; CHECK-NOT: store
; CHECK: ret i32 17

define i32 @test2() {
	%V = load atomic i32* @C seq_cst, align 4
	ret i32 %V
}

; CHECK: define i32 @test2
; CHECK-NOT: load
; CHECK: ret i32 222


; RUN: llvm-as < %s | llc -march=x86-64 &&
; RUN: llvm-as < %s | llc -march=x86-64 | grep GOTPCREL | wc -l | grep 4 &&
; RUN: llvm-as < %s | llc -march=x86-64 | grep rip | wc -l | grep 6 &&
; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | wc -l | grep 6 &&
; RUN: llvm-as < %s | llc -march=x86-64 | grep leaq | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static | grep rip | wc -l | grep 4 &&
; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static | grep movl | wc -l | grep 2 &&
; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=static | grep movq | wc -l | grep 2

%ptr = external global int*
%src = external global [0 x int]
%dst = external global [0 x int]
%lptr = internal global int* null
%ldst = internal global [500 x int] zeroinitializer, align 32
%lsrc = internal global [500 x int] zeroinitializer, align 32
%bsrc = internal global [500000 x int] zeroinitializer, align 32
%bdst = internal global [500000 x int] zeroinitializer, align 32

void %test1() {
	%tmp = load int* getelementptr ([0 x int]* %src, int 0, int 0)
	store int %tmp, int* getelementptr ([0 x int]* %dst, int 0, int 0)
	ret void
}

void %test2() {
	store int* getelementptr ([0 x int]* %dst, int 0, int 0), int** %ptr
	ret void
}

void %test3() {
	store int* getelementptr ([500 x int]* %ldst, int 0, int 0), int** %lptr
	br label %return

return:
	ret void
}


Add a testcase for i256 add. i256 isn't fully supported in codegen right now, but add and subtract work.

; RUN: llvm-as < %s | llc -march=x86 > %t
; RUN: grep adcl %t | count 7
; RUN: grep sbbl %t | count 7

define void @add(i256* %p, i256* %q) nounwind {
  %a = load i256* %p
  %b = load i256* %q
  %c = add i256 %a, %b
  store i256 %c, i256* %p
  ret void
}
define void @sub(i256* %p, i256* %q) nounwind {
  %a = load i256* %p
  %b = load i256* %q
  %c = sub i256 %a, %b
  store i256 %c, i256* %p
  ret void
}


Add a basic test for the SRETPromotion pass.

; RUN: llvm-as < %s | opt -sretpromotion | llvm-dis > %t
; RUN: cat %t | grep sret | count 1

; This function is promotable
define internal void @promotable({i32, i32}* sret %s) {
  %A = getelementptr {i32, i32}* %s, i32 0, i32 0
  store i32 0, i32* %A
  %B = getelementptr {i32, i32}* %s, i32 0, i32 0
  store i32 1, i32* %B
  ret void
}

; This function is not promotable (due to it's use below)
define internal void @notpromotable({i32, i32}* sret %s) {
  %A = getelementptr {i32, i32}* %s, i32 0, i32 0
  store i32 0, i32* %A
  %B = getelementptr {i32, i32}* %s, i32 0, i32 0
  store i32 1, i32* %B
  ret void
}

define void @caller({i32, i32}* %t) {
  %s = alloca {i32, i32}
  call void @promotable({i32, i32}* %s)
  %A = getelementptr {i32, i32}* %s, i32 0, i32 0
  %a = load i32* %A
  %B = getelementptr {i32, i32}* %s, i32 0, i32 0
  %b = load i32* %B
  ; This passes in something that's not an alloca, which makes the argument not
  ; promotable
  call void @notpromotable({i32, i32}* %t)
  ret void
}


Add test that shows that InstCombine can do better

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -instcombine < %s | FileCheck %s
; TODO: The entire thing should be folded to and i16 %0, 255.

define i16 @foo(i16 )  {
; CHECK-LABEL: @foo(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = and i16 [[TMP0:%.*]], 255
; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 255
; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 255
; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; CHECK-NEXT:    [[TMP6:%.*]] = and i16 [[TMP5]], 255
; CHECK-NEXT:    ret i16 [[TMP6]]
;
entry:
  %1 = and i16 %0, 255
  %2 = zext i16 %1 to i32
  %3 = icmp ult i32 %2, 255
  %4 = select i1 %3, i32 %2, i32 255
  %5 = trunc i32 %4 to i16
  %6 = and i16 %5, 255
  ret i16 %6
}


; RUN: opt < %s -argpromotion -S | FileCheck %s
; PR 32917

@b = common local_unnamed_addr global i32 0, align 4
@a = common local_unnamed_addr global i32 0, align 4

define i32 @fn2() local_unnamed_addr {
  %1 = load i32, i32* @b, align 4
  %2 = sext i32 %1 to i64
  %3 = inttoptr i64 %2 to i32*
  call fastcc void @fn1(i32* %3)
  ret i32 undef
}

define internal fastcc void @fn1(i32* nocapture readonly) unnamed_addr {
  %2 = getelementptr inbounds i32, i32* %0, i64 -1
  %3 = load i32, i32* %2, align 4
  store i32 %3, i32* @a, align 4
  ret void
}

; CHECK: getelementptr {{.*}} -1
; CHECK-NOT: getelementptr {{.*}} 4294967295


Add a test for the CPU names that should have been in r223769.

; RUN: llc < %s -o /dev/null -mcpu=prescott
; RUN: llc < %s -o /dev/null -mcpu=nocona
; RUN: llc < %s -o /dev/null -mcpu=core2
; RUN: llc < %s -o /dev/null -mcpu=penryn
; RUN: llc < %s -o /dev/null -mcpu=nehalem
; RUN: llc < %s -o /dev/null -mcpu=westmere
; RUN: llc < %s -o /dev/null -mcpu=sandybridge
; RUN: llc < %s -o /dev/null -mcpu=ivybridge
; RUN: llc < %s -o /dev/null -mcpu=haswell
; RUN: llc < %s -o /dev/null -mcpu=broadwell
; RUN: llc < %s -o /dev/null -mcpu=bonnell
; RUN: llc < %s -o /dev/null -mcpu=silvermont
; RUN: llc < %s -o /dev/null -mcpu=k8
; RUN: llc < %s -o /dev/null -mcpu=opteron
; RUN: llc < %s -o /dev/null -mcpu=athlon64
; RUN: llc < %s -o /dev/null -mcpu=athlon-fx
; RUN: llc < %s -o /dev/null -mcpu=k8-sse3
; RUN: llc < %s -o /dev/null -mcpu=opteron-sse3
; RUN: llc < %s -o /dev/null -mcpu=athlon64-sse3
; RUN: llc < %s -o /dev/null -mcpu=amdfam10
; RUN: llc < %s -o /dev/null -mcpu=barcelona
; RUN: llc < %s -o /dev/null -mcpu=bdver1
; RUN: llc < %s -o /dev/null -mcpu=bdver2
; RUN: llc < %s -o /dev/null -mcpu=bdver3
; RUN: llc < %s -o /dev/null -mcpu=bdver4
; RUN: llc < %s -o /dev/null -mcpu=btver1
; RUN: llc < %s -o /dev/null -mcpu=btver2
; RUN: llc < %s -o /dev/null -mcpu=winchip-c6
; RUN: llc < %s -o /dev/null -mcpu=winchip2
; RUN: llc < %s -o /dev/null -mcpu=c3
; RUN: llc < %s -o /dev/null -mcpu=c3-2
; RUN: llc < %s -o /dev/null -mcpu=geode


Add failing test that shows problems with MSSA update in LoopSimplifyCFG

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; REQUIRES: asserts
; XFAIL: *
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -verify-loop-info -verify-dom-info -verify-loop-lcssa < %s | FileCheck %s

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

; Make sure we update MSSA properly.
define void @test(i32* %a, i32* %b) {
; CHECK-LABEL: @test(

entry:
  br label %for.body

for.body:
  %i = phi i32 [ 0, %entry ], [ %i.inc, %latch ]
  br label %switch.bb

switch.bb:
  switch i2 1, label %default [
    i2 1, label %case
  ]

case:
  br label %latch

default:
  unreachable

latch:
  store i32 %i, i32* %a
  store i32 %i, i32* %b
  %i.inc = add nsw i32 %i, 1
  %exitcond = icmp eq i32 %i.inc, 4
  br i1 %exitcond, label %exit, label %for.body

exit:
  ret void
}


Add an interesting case we already get right.

; RUN: llvm-link -S %s -o - | FileCheck %s

define void @f() {
  ret void
}

; We lazy link @v, which causes llvm.global_ctors to have the corresponding
; entry.
@v = linkonce global i8 42

@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* @v }]

; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* @v }]


; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10
; PR4280

define i32 @__fixunssfsi(float %a) nounwind readnone {
entry:
	%0 = fcmp ult float %a, 0x41E0000000000000		; <i1> [#uses=1]
	br i1 %0, label %bb1, label %bb

bb:		; preds = %entry
	ret i32 1

bb1:		; preds = %entry
	ret i32 0
}


Add missing test case for previous commit.

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s

; Test that we don't abort fast-isle for ret
define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: ret_v8i8
; CHECK:       add.8b v0, v0, v1
  %1 = add <8 x i8> %a, %b
  ret <8 x i8> %1
}


Add a regression test for struct return lowering

; RUN: llc < %s -march=avr | FileCheck %s

; This test ensures that the backend can lower returns of struct values.
; It does not check how these are lowered.
;
; In the past, this code used to return an error
;
; Assertion `InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"' failed.
;
; This feature was first implemented in r325474.

declare i8 @do_something(i8 %val)

; CHECK-LABEL: main
define { i1, i8 } @main(i8) #2 {
entry:
  %1 = call zeroext i8 @do_something(i8 zeroext %0)
  %2 = insertvalue { i1, i8 } { i1 true, i8 undef }, i8 %1, 1
  ret { i1, i8 } %2
}


Add a test for the fix in revision 91009.

; RUN: opt < %s -licm -disable-output
define void @foo (i8* %v)
{
  entry:
    br i1 undef, label %preheader, label %return

  preheader:
    br i1 undef, label %loop, label %return

  loop:
    indirectbr i8* undef, [label %preheader, label %stuff]

  stuff:
    %0 = load i8* undef, align 1
    br label %loop

  return:
    ret void

}


Add test to cover accurate-sample-profile.

; For SamplePGO, if -accurate-sample-profile is specified, cold callsite
; heuristics should be honored if the caller has no profile.

; RUN: opt < %s -inline -S -inline-cold-callsite-threshold=0 | FileCheck %s
; RUN: opt < %s -inline -S -inline-cold-callsite-threshold=0 -accurate-sample-profile | FileCheck %s --check-prefix=ACCURATE

define i32 @callee(i32 %x) {
  %x1 = add i32 %x, 1
  %x2 = add i32 %x1, 1
  %x3 = add i32 %x2, 1
  call void @extern()
  call void @extern()
  ret i32 %x3
}

define i32 @caller(i32 %y1) {
; CHECK-NOT: call i32 @callee
; ACCURATE: call i32 @callee
  %y2 = call i32 @callee(i32 %y1)
  ret i32 %y2
}

declare void @extern()

!llvm.module.flags = !{!1}
!1 = !{i32 1, !"ProfileSummary", !2}
!2 = !{!3, !4, !5, !6, !7, !8, !9, !10}
!3 = !{!"ProfileFormat", !"SampleProfile"}
!4 = !{!"TotalCount", i64 10000}
!5 = !{!"MaxCount", i64 1000}
!6 = !{!"MaxInternalCount", i64 1}
!7 = !{!"MaxFunctionCount", i64 1000}
!8 = !{!"NumCounts", i64 3}
!9 = !{!"NumFunctions", i64 3}
!10 = !{!"DetailedSummary", !11}
!11 = !{!12, !13, !14}
!12 = !{i32 10000, i64 100, i32 1}
!13 = !{i32 999000, i64 100, i32 1}
!14 = !{i32 999999, i64 1, i32 2}


Test that we fail to flatten CFG after forming @llvm.umul.with.overflow

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -S | FileCheck %s

; This is checking that the multiplication does overflow, with a leftover
; guard against division-by-zero that was needed before InstCombine
; produced llvm.umul.with.overflow.

define i1 @will_overflow(i64 %size, i64 %nmemb) {
; CHECK-LABEL: @will_overflow(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[SIZE:%.*]], 0
; CHECK-NEXT:    br i1 [[CMP]], label [[LAND_END:%.*]], label [[LAND_RHS:%.*]]
; CHECK:       land.rhs:
; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[SIZE]], i64 [[NMEMB:%.*]])
; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i64, i1 } [[UMUL]], 1
; CHECK-NEXT:    [[UMUL_NOT_OV:%.*]] = xor i1 [[UMUL_OV]], true
; CHECK-NEXT:    br label [[LAND_END]]
; CHECK:       land.end:
; CHECK-NEXT:    [[TMP0:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[UMUL_NOT_OV]], [[LAND_RHS]] ]
; CHECK-NEXT:    ret i1 [[TMP0]]
;
entry:
  %cmp = icmp eq i64 %size, 0
  br i1 %cmp, label %land.end, label %land.rhs

land.rhs:                                         ; preds = %entry
  %umul = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %size, i64 %nmemb)
  %umul.ov = extractvalue { i64, i1 } %umul, 1
  %umul.not.ov = xor i1 %umul.ov, true
  br label %land.end

land.end:                                         ; preds = %land.rhs, %entry
  %0 = phi i1 [ true, %entry ], [ %umul.not.ov, %land.rhs ]
  ret i1 %0
}

; Function Attrs: nounwind readnone speculatable
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #0


; RUN: llvm-as < %s | llc

@ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00"

define i1 @foo(i32 %v1, i32 %v2) nounwind {
entry:
  %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
  %sum = extractvalue {i32, i1} %t, 0
  %obit = extractvalue {i32, i1} %t, 1
  br i1 %obit, label %overflow, label %normal

normal:
  %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
  ret i1 true

overflow:
  %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
  ret i1 false
}

declare i32 @printf(i8*, ...) nounwind
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)


Make sure that setcc is implemented for bools.

; SetCC on boolean values was not implemented!

; RUN: if as < %s | opt -constprop -die | dis | grep 'set'
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

bool "test1"() {
	%A = setle bool true, false
	%B = setge bool true, false
	%C = setlt bool false, true
	%D = setgt bool true, false
	%E = seteq bool false, false
	%F = setne bool false, true
	%G = and bool %A, %B
	%H = and bool %C, %D
	%I = and bool %E, %F
	%J = and bool %G, %H
	%K = and bool %I, %J
	ret bool %K
}


; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep getelementptr
; PR2831

; Don't raise arbitrary inttoptr+arithmetic+ptrtoint to getelementptr.

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"

define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
	%0 = ptrtoint i8** %argv to i32		; <i32> [#uses=1]
	%1 = add i32 %0, 1		; <i32> [#uses=1]
	ret i32 %1
}

; This testcase could theoretically be optimized down to return zero,
; but for now being conservative with ptrtoint/inttoptr is fine.
define i32 @a() nounwind {
entry:
	%b = alloca i32		; <i32*> [#uses=3]
	%a = alloca i32		; <i32*> [#uses=2]
	%"alloca point" = bitcast i32 0 to i32		; <i32> [#uses=0]
	store i32 1, i32* %b, align 4
	%a1 = ptrtoint i32* %a to i32		; <i32> [#uses=1]
	%b4 = ptrtoint i32* %b to i32		; <i32> [#uses=1]
	%a7 = ptrtoint i32* %a to i32		; <i32> [#uses=1]
	%0 = sub i32 %b4, %a7		; <i32> [#uses=1]
	%1 = add i32 %a1, %0		; <i32> [#uses=1]
	%2 = inttoptr i32 %1 to i32*		; <i32*> [#uses=1]
	store i32 0, i32* %2, align 4
	%3 = load i32* %b, align 4		; <i32> [#uses=1]
	br label %return

return:		; preds = %entry
	ret i32 %3
}


Add a test case for abstract parameter and result types in function definitions. The assembler should produce an error on this input.

; The assembler should catch an undefined argument type .
; RUN: llvm-as < %s -o /dev/null -f 2>&1 | grep "Reference to abstract argument"

; %typedef.bc_struct = type opaque

implementation   ; Functions:

define bool %someFunc(i32* %tmp.71.reload, %typedef.bc_struct* %n1) {
	ret bool true
}


Fix an all too common form of the 'Found global types that are not compatible' warning

; RUN: llvm-as < %s | opt -funcresolve -disable-output 2>&1 | not grep WARNING

void %test() {
  call int(...)* %test()
  ret void
}

declare int %test(...)


; RUN: llc %s -O0 -march=sparc -mcpu=leon3 -mattr=+fixallfdivsqrt -o - | FileCheck %s
; RUN: llc %s -O0 -march=sparc -mcpu=ut699 -o - | FileCheck %s

; CHECK-LABEL: test_1
; CHECK:  nop
; CHECK:  nop
; CHECK:  fdivd
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
define double @test_1(double* byval %a, double* byval %b) {
entry:
    %0 = load double, double* %a, align 8
    %1 = load double, double* %b, align 8
    %res = fdiv double %0, %1
    ret double %res
}

declare double @llvm.sqrt.f64(double) nounwind readonly

; CHECK-LABEL: test_2
; CHECK:  nop
; CHECK:  nop
; CHECK:  nop
; CHECK:  nop
; CHECK:  nop
; CHECK:  fsqrtd
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
; CHECK-NEXT:  nop
define double @test_2(double* byval %a) {
entry:
    %0 = load double, double* %a, align 8
    %1 = call double @llvm.sqrt.f64(double %0) nounwind
    ret double %1
}


Add testcase that checks that DeadArgElim doesn't touch stuff it shouldn't touch.

; RUN: llvm-as < %s | opt -deadargelim | llvm-dis > %t
; RUN: cat %t | grep {define internal \{  \} @test}
; RUN: cat %t | grep {define internal \{ i32 \} @test}
; RUN: cat %t | grep {define internal \<\{ i32, i32 \}\> @test}

; Check if the pass doesn't modify anything that doesn't need changing. We feed
; an unused argument to each function to lure it into changing _something_ about
; the function and then changing to much.

; This checks if the struct retval isn't changed into a void
define internal {  } @test(i32 %DEADARG1) {
        ret {  } {  }
}

; This checks if the struct retval isn't removed
define internal {i32} @test1(i32 %DEADARG1) {
        ret { i32 } { i32 1 }
}

; This checks if the struct doesn't get non-packed
define internal <{ i32, i32 }> @test2(i32 %DEADARG1) {
        ret <{ i32, i32 }> <{ i32 1, i32 2 }>
}

; We use this external function to make sure the return values don't become dead
declare void @user({  }, { i32 }, <{ i32, i32 }>)

define void @caller() {
        %A = call {  } @test(i32 0)
        %B = call { i32 } @test1(i32 1)
        %C = call <{ i32, i32 }> @test2(i32 2)
        call void @user({  } %A, { i32 } %B, <{ i32, i32 }> %C)
        ret void
}


Add another test case for instruction scheduling.

; RUN: llvm-as < %s | llc -march=x86 -stats 2>&1 | grep 'asm-printer' | grep 7

int %g(int %a, int %b) {
	%tmp.1 = shl int %b, ubyte 1
	%tmp.3 = add int %tmp.1, %a
	%tmp.5 = mul int %tmp.3, %a
	%tmp.8 = mul int %b, %b
	%tmp.9 = add int %tmp.5, %tmp.8
	ret int %tmp.9
}


Add a testcase where GVNPRE what getting confused by a loop.

; RUN: llvm-as < %s | opt -gvnpre | llvm-dis

define fastcc void @compute_max_score_1() {
entry:
	%tmp7 = sub i32 0, 0		; <i32> [#uses=0]
	br label %bb

bb:		; preds = %bb212, %entry
	%indvar29 = phi i32 [ 0, %entry ], [ %indvar.next30, %bb212 ]		; <i32> [#uses=2]
	%j.01.0 = sub i32 %indvar29, 0		; <i32> [#uses=0]
	br label %cond_next166

cond_next166:		; preds = %cond_next166, %bb
	br i1 false, label %bb212, label %cond_next166

bb212:		; preds = %cond_next166
	%indvar.next30 = add i32 %indvar29, 1		; <i32> [#uses=1]
	br i1 false, label %return, label %bb

return:		; preds = %bb212
	ret void
}


; RUN: llc -o - %s | FileCheck %s
; This tests for the problem originally reported in http://llvm.org/PR25951
target triple = "i686-unknown-linux-gnu"

@b = common global i8 0, align 1
@c = common global i32 0, align 4
@a = common global i8 0, align 1
@d = common global i8 0, align 1
@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1

; CHECK-LABEL: func:
; This tests whether eax is properly saved/restored around the lahf/sahf
; instruction sequences.
define i32 @func() {
entry:
  %bval = load i8, i8* @b
  %inc = add i8 %bval, 1
  store i8 %inc, i8* @b
  %cval = load i32, i32* @c
  %inc1 = add nsw i32 %cval, 1
  store i32 %inc1, i32* @c
  %aval = load i8, i8* @a
  %inc2 = add i8 %aval, 1
  store i8 %inc2, i8* @a
; Copy flags produced by the incb of %inc1 to a register, need to save+restore
; eax around it. The flags will be reused by %tobool.
; CHECK: pushl %eax
; CHECK: seto %al
; CHECK: lahf
; CHECK: movl %eax, [[REG:%[a-z]+]]
; CHECK: popl %eax
  %cmp = icmp eq i8 %aval, %bval
  %conv5 = zext i1 %cmp to i8
  store i8 %conv5, i8* @d
  %tobool = icmp eq i32 %inc1, 0
; We restore flags with an 'addb, sahf' sequence, need to save+restore eax
; around it.
; CHECK: pushl %eax
; CHECK: movl [[REG]], %eax
; CHECK: addb $127, %al
; CHECK: sahf
; CHECK: popl %eax
  br i1 %tobool, label %if.end, label %if.then

if.then:
  %conv6 = sext i8 %inc to i32
  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %conv6)
  br label %if.end

if.end:
  ret i32 0
}

declare i32 @printf(i8* nocapture readonly, ...)


Add positive test for sqrt "partial inlining". NFC.

; RUN: opt -S -partially-inline-libcalls < %s | FileCheck %s
; RUN: opt -S -passes=partially-inline-libcalls < %s | FileCheck %s

target triple = "x86_64-unknown-linux-gnu"

define float @f(float %val) {
; CHECK: @f
; CHECK: entry:
; CHECK-NEXT: %[[RES:.+]] = tail call float @sqrtf(float %val) #0
; CHECK-NEXT: %[[CMP:.+]] = fcmp oeq float %[[RES]], %[[RES]]
; CHECK-NEXT: br i1 %[[CMP]], label %[[EXIT:.+]], label %[[CALL:.+]]
; CHECK: [[CALL]]:
; CHECK-NEXT: %[[RES2:.+]] = tail call float @sqrtf(float %val){{$}}
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: %[[RET:.+]] = phi float [ %[[RES]], %entry ], [ %[[RES2]], %[[CALL]] ]
; CHECK-NEXT: ret float %[[RET]]
entry:
  %res = tail call float @sqrtf(float %val)
  ret float %res
}

declare float @sqrtf(float)


Make sure to not accidentally get a bogus tail marker

; RUN: llvm-as < %s | opt -inline | llvm-dis | not grep tail

implementation

declare void %bar(int*)

internal void %foo(int* %P) {  ;; to be inlined
  tail call void %bar(int* %P)
  ret void
}

void %caller() {
	%A = alloca int
	call void %foo(int* %A)   ;; not a tail call
	ret void
}


Add a replacement for 2009-02-12-GEPNoalias.ll that works without -debug.

; RUN: llvm-as < %s | opt -aa-eval -basicaa |& grep {0 no alias}

declare noalias i32* @noalias()

define void @test(i32 %x) {
  %a = call i32* @noalias()
  %b = getelementptr i32* %a, i32 %x
  ret void
}


Make sure that pure calls don't kill loads

; RUN: llvm-as < %s | opt -basicaa -load-vn -gcse -instcombine | llvm-dis | not grep sub
declare int %strlen(sbyte*)
declare void %use(int %X)

sbyte %test(sbyte* %P, sbyte* %Q) {
	%A = load sbyte* %Q
	%X = call int %strlen(sbyte* %P)
	%B = load sbyte* %Q                ;; CSE with A.
	call void %use(int %X)             ;; make strlen not dead

	%C = sub sbyte %A, %B
	ret sbyte %C
}


Add a test case for shl of APInt integers > 64 bits by 0 shift amount.

; RUN: llvm-as %s -f -o %t.bc
; RUN: lli -force-interpreter=true %t.bc | tee %t.out | grep 10

; Test that APInt shift left works when bitwidth > 64 and shiftamt == 0

declare i32 @putchar(i32)

define void @putBit(i65 %x, i65 %bitnum) {
  %tmp1 = shl i65 1, %bitnum
  %tmp2 = and i65 %x, %tmp1
  %cond = icmp ne i65 %tmp2, 0
  br i1 %cond, label %cond_true, label %cond_false

cond_true:
  call i32 @putchar(i32 49)
  br label %cond_next

cond_false:
  call i32 @putchar(i32 48)
  br label %cond_next

cond_next:
  ret void
}

define i32 @main() {
  call void @putBit(i65 1, i65 0)
  call void @putBit(i65 0, i65 0)
  ret i32 0
}


Add test that demonstrates buggy behavior on term folding of LoopSimplifyCFG

; This is currently failing because of bug in LoopSimplifyCFG. It does not update
; duplicating Phi inputs properly.
; XFAIL: *
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -passes='require<domtree>,loop(simplify-cfg)' -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s
; RUN: opt -S -enable-loop-simplifycfg-term-folding=true -loop-simplifycfg -enable-mssa-loop-dependency=true -verify-memoryssa -debug-only=loop-simplifycfg -verify-loop-info -verify-dom-info -verify-loop-lcssa 2>&1 < %s | FileCheck %s

target datalayout = "P40"

@a = external global i16, align 1

; CHECK-LABEL: @f1(

define void @f1(i1 %cond) {
entry:
  br label %for.cond

for.cond:
  br i1 %cond, label %if.then, label %for.inc

if.then:
  %0 = load i16, i16* @a, align 1
  %tobool = icmp ne i16 %0, 0
  br i1 %tobool, label %for.inc, label %for.inc

for.inc:
  %c.1 = phi i16 [ 2, %if.then ], [ 2, %if.then ], [ 1, %for.cond ]
  br label %for.cond
}


; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh
; RUN: llc < %s -march=x86    -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh

define void @_Z1fv() {
entry:
	br label %return

return:
	ret void
}


Test case for a SETCC / BRCOND folding bug.

; RUN: llvm-as < %s | llc

target endian = little
target pointersize = 32
	%struct.node_t = type { double*, %struct.node_t*, %struct.node_t**, double**, double*, int, int }

implementation   ; Functions:

void %main() {
entry:
	br bool false, label %then.2.i, label %endif.2.i

then.2.i:		; preds = %entry
	br label %dealwithargs.exit

endif.2.i:		; preds = %entry
	br bool false, label %then.3.i, label %dealwithargs.exit

then.3.i:		; preds = %endif.2.i
	br label %dealwithargs.exit

dealwithargs.exit:		; preds = %then.3.i, %endif.2.i, %then.2.i
	%n_nodes.4 = phi int [ 64, %then.3.i ], [ 64, %then.2.i ], [ 64, %endif.2.i ]		; <int> [#uses=1]
	%tmp.14.i1134.i.i = setgt int %n_nodes.4, 1		; <bool> [#uses=2]
	br bool %tmp.14.i1134.i.i, label %no_exit.i12.i.i, label %fill_table.exit22.i.i

no_exit.i12.i.i:		; preds = %no_exit.i12.i.i, %dealwithargs.exit
	br bool false, label %fill_table.exit22.i.i, label %no_exit.i12.i.i

fill_table.exit22.i.i:		; preds = %no_exit.i12.i.i, %dealwithargs.exit
	%cur_node.0.i8.1.i.i = phi %struct.node_t* [ undef, %dealwithargs.exit ], [ null, %no_exit.i12.i.i ]		; <%struct.node_t*> [#uses=0]
	br bool %tmp.14.i1134.i.i, label %no_exit.i.preheader.i.i, label %make_tables.exit.i

no_exit.i.preheader.i.i:		; preds = %fill_table.exit22.i.i
	ret void

make_tables.exit.i:		; preds = %fill_table.exit22.i.i
	ret void
}


; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"

; CHECK-NOT: MergedGlobals

@a = internal unnamed_addr global i1 false
@b = internal global [64 x i8] zeroinitializer, align 64


Add a test for non most dominating leader.

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
@b = external global i32, align 4
@a = external global i32, align 4
define void @tinkywinky() {
entry:
  br label %l1
l1.loopexit:
  %g.223.lcssa = phi i32* [ @b, %for.body3 ]
  br label %l1
l1:
  %g.0 = phi i32* [ undef, %entry ], [ %g.223.lcssa, %l1.loopexit ]
  %f.0 = phi i32* [ @b, %entry ], [ @a, %l1.loopexit ]
  br label %for.cond
for.cond.loopexit:
  br label %for.cond
for.cond:
  %g.1 = phi i32* [ %g.0, %l1 ], [ %g.4, %for.cond.loopexit ]
  %f.1 = phi i32* [ %f.0, %l1 ], [ %f.2, %for.cond.loopexit ]
  br i1 undef, label %for.end14, label %for.cond1.preheader
for.cond1.preheader:
  br label %for.body3
for.cond1:
  br label %l2
for.body3:
  br i1 undef, label %for.cond1, label %l1.loopexit
l2:
  %g.4 = phi i32* [ %g.1, %for.end14 ], [ @a, %for.cond1 ]
  %f.2 = phi i32* [ %f.1, %for.end14 ], [ @a, %for.cond1 ]
  br label %for.inc
for.inc:
  br i1 false, label %for.cond.loopexit, label %for.inc
for.end14:
  br label %l2
}


Check opaque, abstract, and recursive type handling

; This test case is used to test opaque type processing, forward references,
; and recursive types.  Oh my.
;

%SQ1 = type { int }
%ITy = type opaque
%SQ2 = type { %ITy }
%ITy = type int

%CCC = type { \2* }
%BBB = type { \2*, \2 * }
%AAA = type { \2*, {\2*}, [{\2*}], {[1x{\2*}]} }

; Test numbered types
type %CCC
type %BBB
%Composite = type { %0, %1 }

; Test simple opaque type resolution...
%intty = type opaque
%intty = type int

; Perform a simple forward reference...
%ty1 = type { %ty2, int }
%ty2 = type float

; Do a recursive type...
%list = type { %list * }
%listp = type { %listp } *

; Do two mutually recursive types...
%TyA = type { %ty2, %TyB * }
%TyB = type { double, %TyA * }

; A complex recursive type...
%Y = type { {%Y*}, %Y* }
%Z = type { { %Z * }, [%Z] *, {{{ %Z * }}} }

; More ridiculous test cases...
%A = type [ 123x %A*]
%M = type %M (%M, %M) *
%P = type %P*

; Recursive ptrs
%u = type %v*
%v = type %u*

; Test the parser for unnamed recursive types...
%P1 = type \1 *
%Y1 = type { { \3 * }, \2 * }
%Z1 = type { { \3 * }, [\3] *, { { { \5 * } } } }

implementation


; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux-gnu"

define i64 @PR30511(<2 x double> %a) {
; CHECK:       # BB#0:
; CHECK-NEXT:    addpd {{.*}}(%rip), %xmm0
; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-NEXT:    cvtdq2pd %xmm0, %xmm0
; CHECK-NEXT:    mulpd {{.*}}(%rip), %xmm0
; CHECK-NEXT:    movd %xmm0, %rax
; CHECK-NEXT:    retq
  %1 = fadd <2 x double> %a, <double 0x4338000000000000, double 0x4338000000000000>
  %2 = bitcast <2 x double> %1 to <2 x i64>
  %3 = trunc <2 x i64> %2 to <2 x i32>
  %4 = sitofp <2 x i32> %3 to <2 x double>
  %5 = fmul <2 x double> %4, <double 0x3E76800000000000, double 0x3E76800000000000>
  %6 = extractelement <2 x double> %5, i32 0
  %7 = bitcast double %6 to i64
  ret i64 %7
}


Add some tests for SimplifyCFG's TurnSwitchRangeIntoICmp(). NFC.

; RUN: opt %s -simplifycfg -S | FileCheck %s

declare i32 @f(i32)

define i32 @basic(i32 %x) {
; CHECK-LABEL: @basic
; CHECK: x.off = add i32 %x, -5
; CHECK: %switch = icmp ult i32 %x.off, 3
; CHECK: br i1 %switch, label %a, label %default

entry:
  switch i32 %x, label %default [
    i32 5, label %a
    i32 6, label %a
    i32 7, label %a
  ]
default:
  %0 = call i32 @f(i32 0)
  ret i32 %0
a:
  %1 = call i32 @f(i32 1)
  ret i32 %1
}

define i32 @unreachable(i32 %x) {
; CHECK-LABEL: @unreachable
; CHECK: x.off = add i32 %x, -5
; CHECK: %switch = icmp ult i32 %x.off, 3
; CHECK: br i1 %switch, label %a, label %b

entry:
  switch i32 %x, label %unreachable [
    i32 5, label %a
    i32 6, label %a
    i32 7, label %a
    i32 10, label %b
    i32 20, label %b
    i32 30, label %b
    i32 40, label %b
  ]
unreachable:
  unreachable
a:
  %0 = call i32 @f(i32 0)
  ret i32 %0
b:
  %1 = call i32 @f(i32 1)
  ret i32 %1
}


Debug Info: Fix the SDLoc propagation for a DAGCombiner rule

; RUN: llc -O0 < %s -mtriple=x86_64-unknown | FileCheck %s
; This was extracted from a swift debugger stepping testcase and checks that the
;   fold (zext (load x)) -> (zext (truncate (zextload x)))
; rule propagates the SDLoc of the load to the zextload.

; CHECK: .loc {{.*}} main.swift:100
; CHECK-NOT: .loc
; CHECK: .loc {{.*}} main.swift:200
; CHECK-NOT: .loc
; CHECK: .loc {{.*}} main.swift:300
; CHECK-NOT: .loc
declare void @foo(double)

define i32 @zext_load(i32* %arg) !dbg !30 {
  %1 = bitcast i32* %arg to i8*
  %2 = getelementptr inbounds i8, i8* %1, i32 1
  %3 = load i8, i8* %2, align 1, !dbg !100
  %4 = uitofp i8 %3 to double, !dbg !200
  call void @foo(double %4), !dbg !200
  %5 = zext i8 %3 to i32, !dbg !300
  ret i32 %5
}
!llvm.dbg.cu = !{!1}
!llvm.module.flags = !{!0}

!0 = !{i32 2, !"Debug Info Version", i32 3}
!1 = distinct !DICompileUnit(language: DW_LANG_Swift, file: !3, isOptimized: false, emissionKind: FullDebug)
!2 = !DIModule(scope: null, name: "test", includePath: "", isysroot: "/")
!3 = !DIFile(filename: "main.swift", directory: "/")

!30 = distinct !DISubprogram(name: "main", scope: !2, file: !3, line: 1, type: !31, isLocal: false, isDefinition: true, isOptimized: false, unit: !1)
!31 = !DISubroutineType(types: !32)
!32 = !{}

!100 = !DILocation(line: 100, scope: !30)
!200 = !DILocation(line: 200, scope: !30)
!300 = !DILocation(line: 300, scope: !30)


Add a testcase for a function we cannot legally promote the argument of.

; RUN: llvm-as < %s | opt -argpromotion | llvm-dis | not grep 'load int\* null'

implementation

internal int %callee(bool %C, int* %P) {
	br bool %C, label %T, label %F
T:
	ret int 17
F:
	%X = load int* %P
	ret int %X
}

int %foo() {
	%X = call int %callee(bool true, int* null)
	ret int %X
}


; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s

; Make sure that we don't match this shuffle using the vpblendw instruction.
; The mask for the vpblendw instruction needs to be identical for both halves
; of the YMM.

; CHECK: blendw1
; CHECK-NOT: vpblendw
; CHECK: ret
define <16 x i16> @blendw1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline {
  %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <16 x i16> %t
}


Add a test case for opt -instcombine bug fix in revision 52003.

; RUN: llvm-as < %s | opt -instcombine

define i65 @foo(i65 %x) nounwind  {
entry:
	%tmp2 = ashr i65 %x, 65		; <i65> [#uses=1]
	ret i65 %tmp2
}


Add a test for CodeGenPrepare's ability to look through PHI nodes when performing addressing mode folding, introduced in r119853.

; RUN: llc -march=arm < %s | FileCheck %s
; <rdar://problem/8686347>

define i32 @test1(i1 %a, i32* %b) {
; CHECK: test1
entry:
  br i1 %a, label %lblock, label %rblock

lblock:
  %lbranch = getelementptr i32* %b, i32 1
  br label %end

rblock:
  %rbranch = getelementptr i32* %b, i32 1
  br label %end

end:
; CHECK: ldr	r0, [r1, #4]
  %gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock]
  %r = load i32* %gep
; CHECK-NEXT: bx	lr
  ret i32 %r
}


; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep extsw | wc -l | grep 2

%lens = external global ubyte*
%vals = external global int*

int %test(int %i) {
	%tmp = load ubyte** %lens
	%tmp1 = getelementptr ubyte* %tmp, int %i
	%tmp = load ubyte* %tmp1
	%tmp2 = cast ubyte %tmp to int
	%tmp3 = load int** %vals
	%tmp5 = sub int 1, %tmp2
	%tmp6 = getelementptr int* %tmp3, int %tmp5
	%tmp7 = load int* %tmp6
	ret int %tmp7
}


Add test for constructor and destructor sections.

; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm -o %t.s -f &&
; RUN: grep '\.section \.ctors,"aw",.progbits' %t.s | grep % &&
; RUN: grep '\.section \.dtors,"aw",.progbits' %t.s | grep %

%llvm.global_ctors = appending global [1 x { int, void ()* }] [ { int, void ()* } { int 65535, void ()* %__mf_init } ]		; <[1 x { int, void ()* }]*> [#uses=0]
%llvm.global_dtors = appending global [1 x { int, void ()* }] [ { int, void ()* } { int 65535, void ()* %__mf_fini } ]		; <[1 x { int, void ()* }]*> [#uses=0]

void %__mf_init() {
entry:
	ret void
}

void %__mf_fini() {
entry:
	ret void
}


Test cases for 64-bit multiplication and division.

; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s

define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: dmult
; CHECK: mflo
  %mul = mul i64 %a1, %a0
  ret i64 %mul
}

define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: ddivu
; CHECK: mflo
  %div = udiv i64 %a0, %a1
  ret i64 %div
}

define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: ddiv
; CHECK: mflo
  %div = sdiv i64 %a0, %a1
  ret i64 %div
}

define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: ddivu
; CHECK: mfhi
  %rem = urem i64 %a0, %a1
  ret i64 %rem
}

define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK: ddiv
; CHECK: mfhi
  %rem = srem i64 %a0, %a1
  ret i64 %rem
}


; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10
; Requires: Asserts

; Previously, this would cause an assert.
define i31 @t1(i31 %a, i31 %b, i31 %c) {
entry:
  %add = add nsw i31 %b, %a
  %add1 = add nsw i31 %add, %c
  ret i31 %add1
}


; The purpose of this test is to verify that we do not produce unneeded
; relocations when symbols are in the same section and we know their offset.

; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | coff-dump.py | FileCheck %s
; RUN: llc -filetype=obj -mtriple x86_64-pc-win32 %s -o - | coff-dump.py | FileCheck %s

define void @foo() {
e:
  br label %i
i:
  br label %i
}

define void @bar() {
e:
  br label %i
i:
  br label %i
}

define void @baz() {
e:
  call void @baz()
  ret void
}

; CHECK:     Sections = [
; CHECK-NOT: NumberOfRelocations = {{[^0]}}
; CHECK:     Symbols = [


; RUN: if as < %s | opt -globaldce | dis | grep global
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

%X = uninitialized global int
%Y = internal global int 7


; RUN: llc < %s -O0 -mtriple=thumbv7-apple-darwin

%union.anon = type { <16 x i32> }

@__md0 = external global [137 x i8]

define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
entry:
  ret void
}

define internal i32 @_Z13get_global_idj(i32 %dim) nounwind ssp {
entry:
  ret i32 undef
}

define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp {
entry:
  call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef)
  ret void
}


; RUN: llc -march=mipsel < %s | FileCheck %s

define i32 @foo0() nounwind readnone {
entry:
; CHECK: foo0
; CHECK: lui $[[R0:[0-9]+]], 4660
; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136
  ret i32 305419896
}

define i32 @foo1() nounwind readnone {
entry:
; CHECK: foo1
; CHECK: lui ${{[0-9]+}}, 4660
; CHECK-NOT: ori
  ret i32 305397760
}

define i32 @foo2() nounwind readnone {
entry:
; CHECK: foo2
; CHECK: addiu ${{[0-9]+}}, $zero, 4660
  ret i32 4660
}

define i32 @foo17() nounwind readnone {
entry:
; CHECK: foo17
; CHECK: addiu ${{[0-9]+}}, $zero, -32204
  ret i32 -32204
}

define i32 @foo18() nounwind readnone {
entry:
; CHECK: foo18
; CHECK: ori ${{[0-9]+}}, $zero, 33332
  ret i32 33332
}


; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux < %s | FileCheck %s -check-prefix=CHECK

; Test if the negation of the non-equality check between floating points are
; translated to jnp followed by jne.

; CHECK: jne
; CHECK-NEXT: jnp
define void @foo(float %f) {
entry:
  %cmp = fcmp une float %f, 0.000000e+00
  br i1 %cmp, label %if.then, label %if.end

if.then:
  tail call void @a()
  br label %if.end

if.end:
  ret void
}

declare void @a()


; REQUIRES: asserts
; XFAIL: *
; RUN: opt -passes='unswitch<nontrivial>' -disable-output -S < %s
; RUN: opt -simple-loop-unswitch -enable-nontrivial-unswitch -disable-output -S < %s

; This loop shouldn't trigger asserts in SimpleLoopUnswitch.
define void @test_redundant_switch(i1* %ptr, i32 %cond) {
entry:
  br label %loop_begin

loop_begin:
  switch i32 %cond, label %loop_body [
      i32 0, label %loop_body
  ]

loop_body:
  br label %loop_latch

loop_latch:
  %v = load i1, i1* %ptr
  br i1 %v, label %loop_begin, label %loop_exit

loop_exit:
  ret void
}


Test the new 64bit i64<->fp functionality

; fcfid and fctid should be generated when the 64bit feature is enabled, but not
; otherwise.

; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | grep 'fcfid' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | grep 'fctidz' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep 'fcfid' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep 'fctidz' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | not grep 'fcfid' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | not grep 'fctidz' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | not grep 'fcfid' &&
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | not grep 'fctidz'

double %X(double %Y) {
    %A = cast double %Y to long
    %B = cast long %A to double
	ret double %B
}


Add a BUILD_VECTOR with unpack and interleave testcase.

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep punpckl | wc -l | grep 7

void %test(<8 x short>* %b, short %a0, short %a1, short %a2, short %a3, short %a4, short %a5, short %a6, short %a7) {
	%tmp = insertelement <8 x short> zeroinitializer, short %a0, uint 0
	%tmp2 = insertelement <8 x short> %tmp, short %a1, uint 1
	%tmp4 = insertelement <8 x short> %tmp2, short %a2, uint 2
	%tmp6 = insertelement <8 x short> %tmp4, short %a3, uint 3
	%tmp8 = insertelement <8 x short> %tmp6, short %a4, uint 4
	%tmp10 = insertelement <8 x short> %tmp8, short %a5, uint 5
	%tmp12 = insertelement <8 x short> %tmp10, short %a6, uint 6
	%tmp14 = insertelement <8 x short> %tmp12, short %a7, uint 7
	store <8 x short> %tmp14, <8 x short>* %b
	ret void
}


Add test case to verify correct relocs being generated for TLS symbols on PowerPC using the integrated assembler.

;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj %s -o - | \
;; RUN: elf-dump --dump-section-data | FileCheck %s

;; FIXME: this file should be in .s form, change when asm parser is available.

@t = thread_local global i32 0, align 4

define i32* @f() nounwind {
entry:
  ret i32* @t
}

;; Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
;; against the thread-local symbol 't'.
;; CHECK:       '.rela.text'
;; CHECK:       Relocation 0
;; CHECK-NEXT:  'r_offset',
;; CHECK-NEXT:  'r_sym', 0x00000008
;; CHECK-NEXT:  'r_type', 0x00000048
;; CHECK:       Relocation 1
;; CHECK-NEXT:  'r_offset',
;; CHECK-NEXT:  'r_sym', 0x00000008
;; CHECK-NEXT:  'r_type', 0x00000046

;; Check that we got the correct symbol.
;; CHECK:       Symbol 8
;; CHECK-NEXT:  't'


Test case for PR1137. This makes sure that we don't get erroneous "redefinition" errors that cause the upgrade to fail.

; PR1137
; RUN: llvm-upgrade < %s &&
; RUN: llvm-upgrade < %s | llvm-as -o /dev/null -f &&
; RUN: llvm-upgrade < %s | grep 'tmp = alloca' | wc -l | grep 1
;
target datalayout = "e-p:32:32"
target endian = little
target pointersize = 32
target triple = "i686-pc-linux-gnu"

implementation   ; Functions:

void %main() {
entry:
    %tmp = alloca uint, align 4             ; <uint*> [#uses=1]
    %tmp = alloca int, align 4              ; <int*> [#uses=1]
    "alloca point" = cast int 0 to int      ; <int> [#uses=0]
    store uint 1, uint* %tmp
    store int 2, int* %tmp
    ret void
}


Add a test to ensure a bitcast/and/trunc combination eliminates the bitcast.

; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep bitcast
bool %test1(uint %val) {
  %t1 = bitcast uint %val to int
  %t2 = and int %t1, 1
  %t3 = trunc int %t2 to bool
  ret bool %t3
}

short %test1(uint %val) {
  %t1 = bitcast uint %val to int
  %t2 = and int %t1, 1
  %t3 = trunc int %t2 to short
  ret short %t3
}


Add a test for the LSR issue exposed by r125254.

; RUN: opt < %s -loop-reduce -verify
target triple = "x86_64-apple-darwin10"

define void @myquicksort(i8* %a) nounwind ssp {
entry:
  br i1 undef, label %loop1, label %return

loop1:                                            ; preds = %bb13.loopexit, %entry
  %indvar419 = phi i64 [ %indvar.next420, %loop2.exit ], [ 0, %entry ]
  %tmp474 = shl i64 %indvar419, 2
  %tmp484 = add i64 %tmp474, 4
  br label %loop2

loop2:                                            ; preds = %loop1, %loop2.backedge
  %indvar414 = phi i64 [ %indvar.next415, %loop2.backedge ], [ 0, %loop1 ]
  %tmp473 = mul i64 %indvar414, -4
  %tmp485 = add i64 %tmp484, %tmp473
  %storemerge4 = getelementptr i8* %a, i64 %tmp485
  %0 = icmp ugt i8* %storemerge4, %a
  br i1 false, label %loop2.exit, label %loop2.backedge

loop2.backedge:                                   ; preds = %loop2
  %indvar.next415 = add i64 %indvar414, 1
  br label %loop2

loop2.exit:                                       ; preds = %loop2
  %indvar.next420 = add i64 %indvar419, 1
  br i1 undef, label %loop1, label %return

return:                                           ; preds = %loop2.exit, %entry
  ret void
}


Add a new testcase which breaks the sinker because the loop canonnicalization pass does not do a canonnicalization that the sinker wants.

; This testcase checks to make sure the sinker does not cause problems with
; critical edges.

; RUN: llvm-as < %s | opt -licm | llvm-dis | grep -C1 add | grep Exit

implementation   ; Functions:

void %test() {
Entry:
	br bool false, label %Loop, label %Exit

Loop:
	%X = add int 0, 1
	br bool false, label %Loop, label %Exit

Exit:
	%Y = phi int [ 0, %Entry ], [ %X, %Loop ]
	ret void
}


Add a testcase which got fixed by recent legalization work.

; RUN: llvm-as < %s | llc -march=x86-64
; PR3886

define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
entry:
        %a = call <1 x i64> @bar()
        %tmp5.i = extractelement <1 x i64> %a, i32 0
        %tmp11 = bitcast i64 %tmp5.i to <1 x i64>
        %tmp8 = extractelement <1 x i64> %tmp11, i32 0
        %call6 = call i32 (i64)* @foo(i64 %tmp8)
        ret i32 undef
}

declare i32 @foo(i64)

declare <1 x i64> @bar()


; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64

define zeroext i1 @PR22473(i8*, i8) {
; X86-LABEL: PR22473:
; X86:       # %bb.0:
; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-NEXT:    movb (%eax), %al
; X86-NEXT:    cmpb {{[0-9]+}}(%esp), %al
; X86-NEXT:    sete %al
; X86-NEXT:    retl
;
; X64-LABEL: PR22473:
; X64:       # %bb.0:
; X64-NEXT:    cmpb %sil, (%rdi)
; X64-NEXT:    sete %al
; X64-NEXT:    retq
  %3 = load i8, i8* %0, align 1
  %4 = icmp eq i8 %3, %1
  ret i1 %4
}


Add a test showing when ld64 can hide linkonce_odr symbols.

; RUN: llvm-as %s -o %t.o
; RUN: %ld64 -lto_library %llvmshlibdir/libLTO.dylib -dylib -arch x86_64 -macosx_version_min 10.10.0 -lSystem -o %t.dylib %t.o -save-temps  -undefined dynamic_lookup

; RUN: llvm-dis %t.dylib.lto.opt.bc -o - | FileCheck --check-prefix=IR %s
; check that @a is still a linkonce_odr definition
; IR: define linkonce_odr void @a()

; RUN: llvm-nm %t.dylib | FileCheck --check-prefix=NM %s
; check that the linker can hide @a but not @b
; NM: 0000000000000f10 t _a
; NM: 0000000000000f20 T _b
; NM: 0000000000000f00 T _c

target triple = "x86_64-apple-macosx10.10.0"

declare void @external()

define linkonce_odr void @a() noinline {
  call void @external()
  ret void
}

define linkonce_odr void @b() {
  ret void
}

define void()* @c() {
  call void @a()
  ret void()* @b
}


; RUN: not llvm-as %s -disable-output 2>&1 | FileCheck %s

; CHECK:      function declaration may not have a !dbg attachment
declare !dbg !4 void @f1()

define void @f2() !dbg !4 {
  unreachable
}

; CHECK:      function must have a single !dbg attachment
define void @f3() !dbg !4 !dbg !4 {
  unreachable
}

; CHECK-NOT:  !dbg
; CHECK:      function !dbg attachment must be a subprogram
; CHECK-NEXT: void ()* @bar
; CHECK-NEXT: !{{[0-9]+}} = !{}
define void @bar() !dbg !6 {
  unreachable
}

!llvm.module.flags = !{!0}
!0 = !{i32 2, !"Debug Info Version", i32 3}

!llvm.dbg.cu = !{!1}
!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2)
!2 = !DIFile(filename: "t.c", directory: "/path/to/dir")
!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !2, unit: !1)
!6 = !{}


Make sure this doesn't break when we're improving the isels

; RUN: llvm-as < %s | llc -march=ppc32 | grep 'srwi r., r., 5'

int %eq0(int %a) {
	%tmp.1 = seteq int %a, 0		; <bool> [#uses=1]
	%tmp.2 = cast bool %tmp.1 to int		; <int> [#uses=1]
	ret int %tmp.2
}


Add test for pinsrd and pinsrb instructions.

; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pinsrd | count 1
; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 | grep pinsrb | count 1

define <4 x i32> @t1(i32 %s, <4 x i32> %tmp) nounwind {
        %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
        ret <4 x i32> %tmp1
}

define <16 x i8> @t2(i8 %s, <16 x i8> %tmp) nounwind {
        %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
        ret <16 x i8> %tmp1
}


; RUN: llc  -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16

@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@_ZTIPKc = external constant i8*

define i32 @main() {
; 16: main:
; 16: 	.cfi_startproc
; 16: 	save	$ra, $s0, $s1, 32
; 16:   .cfi_offset 17, -8
; 16: 	.cfi_offset 16, -12
; 16: 	.cfi_offset 31, -4
entry:
  %retval = alloca i32, align 4
  store i32 0, i32* %retval
  %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind
  %0 = bitcast i8* %exception to i8**
  store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** %0
  call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIPKc to i8*), i8* null) noreturn
  unreachable

return:                                           ; No predecessors!
  %1 = load i32* %retval
  ret i32 %1
}

declare i8* @__cxa_allocate_exception(i32)

declare void @__cxa_throw(i8*, i8*, i8*)


Add test case to show missed opportunity to combine a concat_vector into a scalar_to_vector. NFC

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s

define void @PR32957(<2 x float>* %in, <8 x float>* %out) {
; CHECK-LABEL: PR32957:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT:    vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; CHECK-NEXT:    vmovaps %ymm0, (%rsi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %ld = load <2 x float>, <2 x float>* %in, align 8
  %ext = extractelement <2 x float> %ld, i64 0
  %ext2 = extractelement <2 x float> %ld, i64 1
  %ins = insertelement <8 x float> <float undef, float undef, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>, float %ext, i64 0
  %ins2 = insertelement <8 x float> %ins, float %ext2, i64 1
  store <8 x float> %ins2, <8 x float>* %out, align 32
  ret void
}


; RUN: llvm-as < %s | opt -lowerinvoke -disable-output &&
; RUN: llvm-as < %s | opt -lowerinvoke -disable-output -enable-correct-eh-support

implementation

int %foo() {
	invoke int %foo() to label %Ok unwind label %Crap
Ok:
	invoke int %foo() to label %Ok2 unwind label %Crap
Ok2:
	ret int 2
Crap:
	ret int 1
}

int %bar(int %blah) {
	br label %doit
doit:
	;; Value live across an unwind edge.
	%B2 = add int %blah, 1
	invoke int %foo() to label %Ok unwind label %Crap
Ok:
	invoke int %foo() to label %Ok2 unwind label %Crap
Ok2:
	ret int 2
Crap:
	ret int %B2
}


Add new test to make sure simplifycfg doesn't leave around trivially dead instructions.

; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep seteq

; Check that simplifycfg deletes a dead 'seteq' instruction when it
; folds a conditional branch into a switch instruction.

declare void %foo()
declare void %bar()

void %testcfg(uint %V) {
	%C = seteq uint %V, 18
	%D = seteq uint %V, 180
	%E = or bool %C, %D
	br bool %E, label %L1, label %Sw
Sw:
       switch uint %V, label %L1 [
              uint 15, label %L2
              uint 16, label %L2
        ]
L1:
	call void %foo()
	ret void
L2:
	call void %bar()
	ret void
}


Add a simple test to make sure getModRefInfo is 1/2 way sane.

; RUN: llvm-as < %s | opt -print-all-alias-modref-info -aa-eval -disable-output 2>&1 | not grep NoModRef

int %callee() {
  %X = alloca struct { int, int }
  %Y = int* getelementptr struct { int, int }*, uint 1
  %Z = int load struct { int, int }*
  ret %Z
}

int %caller() {
  %X = int callee();
}


; REQUIRES: asserts
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -o /dev/null -debug-only=isel 2>&1 | FileCheck %s

; Make sure we emit the basic block exports and the TokenFactor before the
; inlineasm_br. Not sure how to get a MachineIR change so this reads the debug
; output from SelectionDAG.

; CHECK: t0: ch = EntryToken
; CHECK-NEXT: t4: i32,ch = CopyFromReg t0, Register:i32 %3
; CHECK-NEXT: t10: i32 = add t4, Constant:i32<1>
; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10
; CHECK-NEXT: t6: i32,ch = CopyFromReg t0, Register:i32 %4
; CHECK-NEXT: t13: i32 = add t6, Constant:i32<1>
; CHECK-NEXT: t15: ch = CopyToReg t0, Register:i32 %1, t13
; CHECK-NEXT: t17: ch = TokenFactor t12, t15
; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
; CHECK-NEXT: t8: i32 = add t2, Constant:i32<4>
; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, {{.*}}, t22:1

define i32 @test(i32 %a, i32 %b, i32 %c) {
entry:
  %0 = add i32 %a, 4
  %1 = add i32 %b, 1
  %2 = add i32 %c, 1
  callbr void asm "xorl $0, $0; jmp ${1:l}", "r,X,~{dirflag},~{fpsr},~{flags}"(i32 %0, i8* blockaddress(@test, %fail)) to label %normal [label %fail]

normal:
  ret i32 %1

fail:
  ret i32 %2
}


Add some tests checking that the verifier rejects cases where a definition doesn't dominate a use.

; RUN: not llvm-as < %s -o /dev/null |& FileCheck %s

define i32 @f1(i32 %x) {
       %y = add i32 %z, 1
       %z = add i32 %x, 1
       ret i32 %y
; CHECK: Instruction does not dominate all uses!
; CHECK-NEXT:  %z = add i32 %x, 1
; CHECK-NEXT:  %y = add i32 %z, 1
}

declare i32 @g()
define void @f2(i32 %x) {
bb0:
  %y1 = invoke i32 @g() to label %bb1 unwind label %bb2
bb1:
  ret void
bb2:
  %y2 = phi i32 [%y1, %bb0]
  %y3 = landingpad i32 personality i32 ()* @g
          cleanup
  ret void
; CHECK: Invoke result not available in the unwind destination!
; CHECK-NEXT:  %y1 = invoke i32 @g()
; CHECK-NEXT:        to label %bb1 unwind label %bb2
; CHECK-NEXT:  %y2 = phi i32 [ %y1, %bb0 ]
}

define void @f3(i32 %x) {
bb0:
  %y1 = invoke i32 @g() to label %bb1 unwind label %bb2
bb1:
  ret void
bb2:
  %y2 = landingpad i32 personality i32 ()* @g
          cleanup
  br label %bb3
bb3:
  %y3 = phi i32 [%y1, %bb2]
  ret void
; CHECK: Invoke result does not dominate all uses!
; CHECK-NEXT:  %y1 = invoke i32 @g()
; CHECK-NEXT:          to label %bb1 unwind label %bb2
; CHECK-NEXT:  %y3 = phi i32 [ %y1, %bb2 ]
}

define void @f4(i32 %x) {
bb0:
  br label %bb1
bb1:
  %y3 = phi i32 [%y1, %bb0]
  %y1 = add i32 %x, 1
  ret void
; CHECK: Instruction does not dominate all uses!
; CHECK-NEXT:  %y1 = add i32 %x, 1
; CHECK-NEXT:  %y3 = phi i32 [ %y1, %bb0 ]
}


Add a test case for sext bug that Leo found.

; RUN: llvm-as %s -o - | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN: diff %t1.ll %t2.ll
; RUN: llvm-as < %s | lli --force-interpreter=true | grep -- '-255'

%ARRAY   = global [ 20 x i17 ] zeroinitializer
%FORMAT  = constant [ 4 x i8 ] c"%d\0A\00"

declare i32 %printf(i8* %format, ...)

define void %multiply(i32 %index, i32 %X, i32 %Y) {
  %Z = mul i32 %X, %Y
  %P = getelementptr [20 x i17]* %ARRAY, i32 0, i32 %index
  %Result = trunc i32 %Z to i17
  store i17 %Result, i17* %P
  ret void
}

define i32 %main(i32 %argc, i8** %argc) {
  %i = bitcast i32 0 to i32
  call void %multiply(i32 %i, i32 -1, i32 255)
  %P = getelementptr [20 x i17]* %ARRAY, i32 0, i32 0
  %X = load i17* %P
  %result = sext i17 %X to i32
  %fmt = getelementptr [4 x i8]* %FORMAT, i32 0, i32 0
  call i32 (i8*,...)* %printf(i8* %fmt, i32 %result)
  ret i32 %result
}


; RUN: opt %s -S -disable-basicaa -cfl-steens-aa -aa-eval -print-all-alias-modref-info 2>&1 | FileCheck %s
;
; Regression: we weren't properly checking constexpr selects.

@g = extern_weak dso_local global i32, align 4
@g2 = extern_weak dso_local global i32, align 4
@g3 = extern_weak dso_local global i32, align 4

; CHECK-LABEL: Function: foo
; CHECK: NoAlias: i32* select (i1 icmp ne (i32* @g, i32* null), i32* @g2, i32* @g3), i32** %a
; CHECK: NoAlias: i32* %b, i32** %a
; CHECK: MayAlias: i32* %b, i32* select (i1 icmp ne (i32* @g, i32* null), i32* @g2, i32* @g3)
; CHECK: NoAlias: i32* @g2, i32** %a
; CHECK: MayAlias: i32* @g2, i32* select (i1 icmp ne (i32* @g, i32* null), i32* @g2, i32* @g3)
; CHECK: MayAlias: i32* %b, i32* @g2
; CHECK: NoAlias: i32* @g3, i32** %a
; CHECK: MayAlias: i32* @g3, i32* select (i1 icmp ne (i32* @g, i32* null), i32* @g2, i32* @g3)
; CHECK: MayAlias: i32* %b, i32* @g3
; CHECK: MayAlias: i32* @g2, i32* @g3

define void @foo() {
entry:
  %a = alloca i32*, align 8
  store i32* select (i1 icmp ne (i32* @g, i32* null), i32* @g2, i32* @g3), i32** %a
  %b = load i32*, i32** %a
  %c = load i32, i32* %b
  %d = load i32, i32* @g2
  %e = load i32, i32* @g3
  ret void
}


; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-pc-windows | FileCheck %s

; We should be able to prodcue a single 128-bit load for these two 64-bit loads.
; But we previously weren't because we weren't consistently looking through
; WrapperRIP.

@f = local_unnamed_addr global [4 x float] zeroinitializer, align 16
@ms = common local_unnamed_addr global <4 x float> zeroinitializer, align 16

define void @foo2() {
; CHECK-LABEL: foo2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT:    movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
; CHECK-NEXT:    movapd %xmm0, {{.*}}(%rip)
; CHECK-NEXT:    retq
entry:
  %0 = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([4 x float], [4 x float]* @f, i64 0, i64 2) to <2 x float>*), align 8
  %shuffle.i10 = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %1 = load <2 x float>, <2 x float>* bitcast ([4 x float]* @f to <2 x float>*), align 16
  %shuffle.i7 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %shuffle.i = shufflevector <4 x float> %shuffle.i7, <4 x float> %shuffle.i10, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %shuffle.i, <4 x float>* @ms, align 16
  ret void
}


Check in old testcase sitting in my tree

%MidFnTy = type void (\2*)

implementation

int %main() {
	call %MidFnTy* %Mid(%MidFnTy* %Mid)
	ret int 0
}

internal void %Mid(%MidFnTy *%F) {
	call void %Bottom(%MidFnTy* %F)
	ret void
}

internal void %Bottom(%MidFnTy* %F) {
	call void %F(%MidFnTy* %Mid)
	ret void
}


;test for ADDC and ADDE expansion
;
; RUN: llvm-as < %s | llc -march=alpha -o %t.s -f
; XFAIL: *

define i128 @add128(i128 %x, i128 %y) {
entry:
	%tmp = add i128 %y, %x
	ret i128 %tmp
}


Add a testcase to verify that commands don't crash when they hit errors on stderr.

; RUN: sh -c "\
; RUN:        opt --reject-this-option 2>&-; echo $?; \
; RUN:        opt -o /dev/null /dev/null 2>&-; echo $?; \
; RUN:       " | FileCheck %s
; CHECK: {{^1$}}
; CHECK: {{^0$}}

; Test that the error handling when writing to stderr fails exits the
; program cleanly rather than aborting.


Add testcase for legalizing ISD::CTTZ efficiently. On PPC, ctlz(int) is now codegen'd as this:

; Make sure this testcase does not use ctpop
; RUN: llvm-as < %s | llc -march=ppc32 | grep -i 'cntlzw'

declare int %llvm.cttz(int)

implementation   ; Functions:

int %bar(int %x) {
entry:
	%tmp.1 = call int %llvm.cttz( int %x )
	ret int %tmp.1
}


; RUN: opt -S -sink < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define void @test1(i32* ()*) {
entry:
  %1 = call i32* %0() #0
  fence singlethread seq_cst
  %2 = load i32, i32* %1, align 4
  fence singlethread seq_cst
  %3 = icmp eq i32 %2, 0
  br i1 %3, label %fail, label %pass

fail:                                             ; preds = %top
  br label %pass

pass:                                             ; preds = %fail, %top
  ret void
}

; CHECK-LABEL: @test1(
; CHECK:  %[[call:.*]] = call i32* %0()
; CHECK:  fence singlethread seq_cst
; CHECK:  load i32, i32* %[[call]], align 4
; CHECK:  fence singlethread seq_cst

attributes #0 = { nounwind readnone }


Add a test for r267655: Support "preserving" the summary information when using setModule() API in LTOCodeGenerator

; RUN: opt  -module-summary  < %s > %t1
; RUN: llvm-lto -save-merged-module -exported-symbol=_main -set-merged-module -o %t2 %t1
; RUN: llvm-bcanalyzer -dump %t2.merged.bc | FileCheck %s
; Verify that the module includes the ThinLTO informations
; CHECK: GLOBALVAL_SUMMARY_BLOCK

target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.10.0"

; CHECK: _main
; CHECK: movl $132
define i32 @_Z3fooi(i32 %a) {
entry:
  %a.addr = alloca i32, align 4
  store i32 %a, i32* %a.addr, align 4
  %0 = load i32, i32* %a.addr, align 4
  %1 = load i32, i32* %a.addr, align 4
  %call = call i32 @_Z4bar2i(i32 %1)
  %add = add nsw i32 %0, %call
  ret i32 %add
}

define i32 @_Z4bar2i(i32 %a) {
entry:
  %a.addr = alloca i32, align 4
  store i32 %a, i32* %a.addr, align 4
  %0 = load i32, i32* %a.addr, align 4
  %mul = mul nsw i32 2, %0
  ret i32 %mul
}

define i32 @main() {
entry:
  %retval = alloca i32, align 4
  store i32 0, i32* %retval
  %call = call i32 @_Z3fooi(i32 44)
  ret i32 %call
}


Add a test showing that lto produces relaxable relocations.

; RUN: llvm-as %s -o %t.o
; RUN: ld.lld -m elf_x86_64 -save-temps -shared %t.o -o %t.so
; RUN: llvm-readobj -r %t.so.lto.o | FileCheck %s

; Test that we produce R_X86_64_REX_GOTPCRELX instead of R_X86_64_GOTPCREL
; CHECK: R_X86_64_REX_GOTPCRELX foo

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@foo = external global i32
define i32 @bar() {
  %t = load i32, i32* @foo
  ret i32 %t
}


; RUN: opt -S -codegenprepare %s -o - | FileCheck %s
;
; Ensure that we don't {crash,return a bad value} when given an alloca larger
; than what a pointer can represent.

target datalayout = "p:16:16"

; CHECK-LABEL: @alloca_overflow_is_unknown(
define i16 @alloca_overflow_is_unknown() {
  %i = alloca i8, i32 65537
  %j = call i16 @llvm.objectsize.i16.p0i8(i8* %i, i1 false, i1 false)
  ; CHECK: ret i16 -1
  ret i16 %j
}

declare i16 @llvm.objectsize.i16.p0i8(i8*, i1, i1)


Add a test showing how we handle overaligned allocas w/ no-realign-stack

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=skylake | FileCheck %s

declare void @capture(i64*)

define void @test_natural() "no-realign-stack" {
; CHECK-LABEL: test_natural:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    movq %rsp, %rdi
; CHECK-NEXT:    callq capture
; CHECK-NEXT:    popq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
  %a = alloca i64
  call void @capture(i64* %a)
  ret void
}

define void @test_realign() {
; CHECK-LABEL: test_realign:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pushq %rbp
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    .cfi_offset %rbp, -16
; CHECK-NEXT:    movq %rsp, %rbp
; CHECK-NEXT:    .cfi_def_cfa_register %rbp
; CHECK-NEXT:    andq $-64, %rsp
; CHECK-NEXT:    subq $64, %rsp
; CHECK-NEXT:    movq %rsp, %rdi
; CHECK-NEXT:    callq capture
; CHECK-NEXT:    movq %rbp, %rsp
; CHECK-NEXT:    popq %rbp
; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
; CHECK-NEXT:    retq
  %a = alloca i64, align 64
  call void @capture(i64* %a)
  ret void
}

define void @test_norealign() "no-realign-stack" {
; CHECK-LABEL: test_norealign:
; CHECK:       # %bb.0:
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    movq %rsp, %rdi
; CHECK-NEXT:    callq capture
; CHECK-NEXT:    popq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
  %a = alloca i64, align 64
  call void @capture(i64* %a)
  ret void
}


Add a test to ensure that obvious link messages are actually produced on the standard error.

; Test that linking two files with the same definition causes an error and
; that error is printed out.
; RUN: llvm-as %s -o %t.one.bc -f
; RUN: llvm-as %s -o %t.two.bc -f
; RUN: ignore llvm-ld -disable-opt -link-as-library %t.one.bc %t.two.bc \
; RUN:   -o %t.bc 2>%t.err
; RUN: grep "Function is already defined" %t.err

define i32 @bar() {
	ret i32 0
}


; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufps

void %test_v4sf(<4 x float>* %P, float %X, float %Y) {
	%tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0
	%tmp2 = insertelement <4 x float> %tmp, float %X, uint 1
	%tmp4 = insertelement <4 x float> %tmp2, float %Y, uint 2
	%tmp6 = insertelement <4 x float> %tmp4, float %Y, uint 3
	store <4 x float> %tmp6, <4 x float>* %P
	ret void
}


; RUN: llvm-as < %s | llc -march=x86

void %_ZN13QFSFileEngine4readEPcx() {
	%tmp201 = load int* null
	%tmp201 = cast int %tmp201 to long
	%tmp202 = load long* null
	%tmp203 = add long %tmp201, %tmp202
	store long %tmp203, long* null
	ret void
}


; RUN: if as < %s | opt -adce -simplifycfg | dis | grep then:
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi

void %dead_test8(int* %data.1, int %idx.1) {
entry:		; No predecessors!
	%tmp.1 = load int* %data.1		; <int> [#uses=2]
	%tmp.41 = setgt int %tmp.1, 0		; <bool> [#uses=1]
	br bool %tmp.41, label %no_exit.preheader, label %return

no_exit.preheader:		; preds = %entry
	%tmp.11 = getelementptr int* %data.1, long 1		; <int*> [#uses=1]
	%tmp.22-idxcast = cast int %idx.1 to long		; <long> [#uses=1]
	%tmp.28 = getelementptr int* %data.1, long %tmp.22-idxcast		; <int*> [#uses=1]
	br label %no_exit

no_exit:		; preds = %no_exit.preheader, %endif
	%k.1 = phi int [ %k.0, %endif ], [ 0, %no_exit.preheader ]		; <int> [#uses=3]
	%i.0 = phi int [ %inc.1, %endif ], [ 0, %no_exit.preheader ]		; <int> [#uses=1]
	%tmp.12 = load int* %tmp.11		; <int> [#uses=1]
	%tmp.14 = sub int 0, %tmp.12		; <int> [#uses=1]
	%tmp.161 = setne int %k.1, %tmp.14		; <bool> [#uses=1]
	br bool %tmp.161, label %then, label %else

then:		; preds = %no_exit
	%inc.0 = add int %k.1, 1		; <int> [#uses=1]
	br label %endif

else:		; preds = %no_exit
	%dec = add int %k.1, -1		; <int> [#uses=1]
	br label %endif

endif:		; preds = %else, %then
	%k.0 = phi int [ %dec, %else ], [ %inc.0, %then ]		; <int> [#uses=1]
	store int 2, int* %tmp.28
	%inc.1 = add int %i.0, 1		; <int> [#uses=2]
	%tmp.4 = setlt int %inc.1, %tmp.1		; <bool> [#uses=1]
	br bool %tmp.4, label %no_exit, label %return

return:		; preds = %entry, %endif
	ret void
}


; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s

; This is a case where we would incorrectly conclude that LBB0_1 could only
; be reached via fall through and would therefore omit the label.

; CHECK:      jne     .LBB0_1
; CHECK-NEXT: jnp     .LBB0_3
; CHECK-NEXT: .LBB0_1:

define void @xyz() {
entry:
  br i1 fcmp oeq (double fsub (double undef, double undef), double 0.000000e+00), label %bar, label %foo

foo:
  br i1 fcmp ogt (double fdiv (double fsub (double fmul (double undef, double undef), double fsub (double undef, double undef)), double fmul (double undef, double undef)), double 1.0), label %foo, label %bar

bar:
  ret void
}


Add a test showing the ppc code sequence for getting a function pointer.

; RUN: llc -mtriple powerpc64-linux < %s | FileCheck %s

define void @foo()  {
  ret void
}
declare i32 @bar(i8*)

; CHECK-LABEL: {{^}}zed:
; CHECK:        addis 3, 2, .LC1@toc@ha
; CHECK-NEXT:   ld 3, .LC1@toc@l(3)
; CHECK-NEXT:   bl bar

; CHECK-LABEL: .section        .toc,"aw",@progbits
; CHECK:       .LC1:
; CHECK-NEXT:  .tc foo[TC],foo

define  void @zed() {
  call i32 @bar(i8* bitcast (void ()* @foo to i8*))
  ret void
}


Add testcase for new feature for simplifycfg pass

; Test merging of blocks that only have PHI nodes in them
;
; RUN: if as < %s | opt -simplifycfg | dis | grep 'N:'
; RUN: then exit 1
; RUN: else exit 0
; RUN: fi
;

int %test(bool %a, bool %b) {
        br bool %a, label %M, label %O

O:
	br bool %b, label %N, label %Q
Q:
	br label %N
N:
	%Wp = phi int [0, %O], [1, %Q]
	; This block should be foldable into M
	br label %M

M:
	%W = phi int [%Wp, %N], [2, %0]
	%R = add int %W, 1
	ret int %R
}


Add a testcase for the GlobalOpt inbounds fix.

; RUN: llvm-as < %s | opt -globalopt | llvm-dis | FileCheck %s

; Don't get fooled by the inbounds keyword; it doesn't change
; the computed address.

; CHECK: @H = global i32 2
; CHECK: @I = global i32 2

@llvm.global_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @CTOR } ]
@addr = external global i32
@G = internal global [6 x [5 x i32]] zeroinitializer
@H = global i32 80
@I = global i32 90

define internal void @CTOR() {
  store i32 1, i32* getelementptr ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
  store i32 2, i32* getelementptr inbounds ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
  %t = load i32* getelementptr ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
  store i32 %t, i32* @H
  %s = load i32* getelementptr inbounds ([6 x [5 x i32]]* @G, i64 0, i64 0, i64 0)
  store i32 %s, i32* @I
  ret void
}


Check to make sure that the CFString's back store ends up in the correct section.

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; <rdar://problem/10564621>

%0 = type opaque
%struct.NSConstantString = type { i32*, i32, i8*, i32 }

; Make sure that the string ends up the the correct section.

; CHECK:        .section __TEXT,__cstring
; CHECK-NEXT: l_.str3:

; CHECK:        .section  __DATA,__cfstring
; CHECK-NEXT:   .align  4
; CHECK-NEXT: L__unnamed_cfstring_4:
; CHECK-NEXT:   .quad  ___CFConstantStringClassReference
; CHECK-NEXT:   .long  1992
; CHECK-NEXT:   .space  4
; CHECK-NEXT:   .quad  l_.str3
; CHECK-NEXT:   .long  0
; CHECK-NEXT:   .space  4

@isLogVisible = global i8 0, align 1
@__CFConstantStringClassReference = external global [0 x i32]
@.str3 = linker_private unnamed_addr constant [1 x i8] zeroinitializer, align 1
@_unnamed_cfstring_4 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([1 x i8]* @.str3, i32 0, i32 0), i32 0 }, section "__DATA,__cfstring"
@null.array = weak_odr constant [1 x i8] zeroinitializer, align 1

define linkonce_odr void @bar() nounwind ssp align 2 {
entry:
  %stack = alloca i8*, align 4
  %call = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* null, i8* null, %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_4 to %0*))
  store i8* getelementptr inbounds ([1 x i8]* @null.array, i32 0, i32 0), i8** %stack, align 4
  ret void
}

declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind


Add a testcase for the recent "handle variable vector insert elt in mem" patch


Test dag xform: Fold C ? 0 : 1 to ~C or zext(~C) or trunc(~C)

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep cmov
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep xor
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movzbl | count 1

@r1 = weak global i32 0

define void @t1(i32 %a, double %b) {
  %tmp114 = fcmp ugt double %b, 1.000000e-09
  %tmp120 = icmp eq i32 %a, 0		; <i1> [#uses=1]
  %bothcond = or i1 %tmp114, %tmp120		; <i1> [#uses=1]
  %storemerge = select i1 %bothcond, i32 0, i32 1		; <i32> [#uses=2]
  store i32 %storemerge, i32* @r1, align 4
  ret void
}

@r2 = weak global i8 0

define void @t2(i32 %a, double %b) {
  %tmp114 = fcmp ugt double %b, 1.000000e-09
  %tmp120 = icmp eq i32 %a, 0		; <i1> [#uses=1]
  %bothcond = or i1 %tmp114, %tmp120		; <i1> [#uses=1]
  %storemerge = select i1 %bothcond, i8 0, i8 1		; <i32> [#uses=2]
  store i8 %storemerge, i8* @r2, align 4
  ret void
}


Add a basic testcase for TBAA-aware LICM.

; RUN: opt -tbaa -licm -enable-tbaa -S < %s | FileCheck %s

; LICM should be able to hoist the address load out of the loop
; by using TBAA information.

; CHECK:      entry:
; CHECK-NEXT:   %tmp3 = load double** @P, !tbaa !0
; CHECK-NEXT:   br label %for.body

@P = common global double* null

define void @foo(i64 %n) nounwind {
entry:
  br label %for.body

for.body:                                         ; preds = %entry, %for.body
  %i.07 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
  %tmp3 = load double** @P, !tbaa !1
  %scevgep = getelementptr double* %tmp3, i64 %i.07
  %tmp4 = load double* %scevgep, !tbaa !2
  %mul = fmul double %tmp4, 2.300000e+00
  store double %mul, double* %scevgep, !tbaa !2
  %inc = add i64 %i.07, 1
  %exitcond = icmp eq i64 %inc, %n
  br i1 %exitcond, label %for.end, label %for.body

for.end:                                          ; preds = %for.body, %entry
  ret void
}

!0 = metadata !{metadata !"root", null}
!1 = metadata !{metadata !"pointer", metadata !0}
!2 = metadata !{metadata !"double", metadata !0}


Add a test showing how the Leh_func_endN symbol is used.

; RUN: llc -mtriple x86_64-apple-darwin %s -o - | FileCheck %s
@_ZTIi = external constant i8*

define i32 @main() uwtable optsize ssp {
entry:
  invoke void @_Z1fv() optsize
          to label %try.cont unwind label %lpad

lpad:
  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
          catch i8* bitcast (i8** @_ZTIi to i8*)
  br label %eh.resume

try.cont:
  ret i32 0

eh.resume:
  resume { i8*, i32 } %0
}

declare void @_Z1fv() optsize

declare i32 @__gxx_personality_v0(...)

; CHECK: Leh_func_end0:
; CHECK: GCC_except_table0
; CHECK: = Leh_func_end0-


Add test case to check that calls to mcount follow long calls / short calls options. NFC

; Check call to mcount in case of long/short call options.
; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
; RUN:   | FileCheck -check-prefixes=CHECK,LONG %s
; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
; RUN:   | FileCheck -check-prefixes=CHECK,SHORT %s

; Function Attrs: noinline nounwind optnone
define void @foo() #0 {
entry:
  ret void

; CHECK-LABEL: foo
; LONG:          lui     $1, %hi(_mcount)
; LONG-NEXT:     addiu   $25, $1, %lo(_mcount)
; LONG-NEXT:     jalr    $25
; SHORT:         jal     _mcount
}

attributes #0 = { "instrument-function-entry-inlined"="_mcount" }


Add a new test case for 'undef' shuffles.

; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 &&
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shufps

void %test(<4 x float>* %res, <4 x float>* %A) {
	%tmp1 = load <4 x float>* %A
	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x uint> < uint 0, uint 5, uint 6, uint 7 >
	store <4 x float> %tmp2, <4 x float>* %res
	ret void
}


Test for 241794 (nest attribute in AArch64)

; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s

; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register.

define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver:
; CHECK-NEXT: // BB#0:
; CHECK-NEXT: mov x0, x18
; CHECK-NEXT: ret

  ret i8* %arg
}

define i8* @nest_caller(i8* %arg) nounwind {
; CHECK-LABEL: nest_caller:
; CHECK: mov x18, x0
; CHECK-NEXT: bl nest_receiver
; CHECK: ret

  %result = call i8* @nest_receiver(i8* nest %arg)
  ret i8* %result
}


Add a test case for PR3779: when to promote the function return value.

; RUN: llvm-as < %s | llc -march=x86 | grep movzbl | count 1
; rdar://6699246

define signext i8 @t1(i8* %A) nounwind readnone ssp {
entry:
        %0 = icmp ne i8* %A, null
        %1 = zext i1 %0 to i8
        ret i8 %1
}

define i8 @t2(i8* %A) nounwind readnone ssp {
entry:
        %0 = icmp ne i8* %A, null
        %1 = zext i1 %0 to i8
        ret i8 %1
}


Test to make sure we can SCCP load instructions

; This test makes sure that these instructions are properly constant propagated.
;

; RUN: llvm-as < %s | opt -sccp | llvm-dis | not grep load

%X = constant int 42
%Y = constant [2 x { int, float }] [ { int, float } { int 12, float 1.0 },
                                     { int, float } { int 37, float 1.2312 } ]
int %test1() {
	%B = load int* %X
	ret int %B
}

float %test2() {
	%A = getelementptr [2 x { int, float}]* %Y, long 0, long 1, ubyte 1
	%B = load float* %A
	ret float %B
}

int %test3() {
	%A = getelementptr [2 x { int, float}]* %Y, long 0, long 0, ubyte 0
	%B = load int* %A
	ret int %B
}


Add testcase forgotten in the 214072 commit.

; RUN: llc -march=ppc64 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
; RUN: llc -march=ppc64 -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
; RUN: llc -march=ppc64 -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2
; RUN: llc -march=ppc64le < %s | FileCheck %s -check-prefix=CHECK-ELFv2
; RUN: llc -march=ppc64le -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1
; RUN: llc -march=ppc64le -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2

; CHECK-ELFv2: .abiversion 2
; CHECK-ELFv1-NOT: .abiversion 2


; RUN: llvm-as < %s | llc -march=x86
	%struct.function = type opaque
	%struct.lang_decl = type opaque
	%struct.location_t = type { sbyte*, int }
	%struct.rtx_def = type opaque
	%struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, ubyte, ubyte, ubyte, ubyte, ubyte }
	%struct.tree_decl = type { %struct.tree_common, %struct.location_t, uint, %struct.tree_node*, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, uint, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, int, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, long, %struct.lang_decl* }
	%struct.tree_decl_u1 = type { long }
	%struct.tree_decl_u2 = type { %struct.function* }
	%struct.tree_node = type { %struct.tree_decl }
	%union.tree_ann_d = type opaque

void %check_format_arg() {
	br bool false, label %cond_next196, label %bb12.preheader

bb12.preheader:
	ret void

cond_next196:
	br bool false, label %cond_next330, label %cond_true304

cond_true304:
	ret void

cond_next330:
	br bool false, label %cond_next472, label %bb441

bb441:
	ret void

cond_next472:
	%tmp490 = load %struct.tree_node** null
	%tmp492 = getelementptr %struct.tree_node* %tmp490, int 0, uint 0, uint 0, uint 3
	%tmp492 = cast ubyte* %tmp492 to uint*
	%tmp493 = load uint* %tmp492
	%tmp495 = cast uint %tmp493 to ubyte
	%tmp496 = seteq ubyte %tmp495, 11
	%tmp496 = cast bool %tmp496 to sbyte
	store sbyte %tmp496, sbyte* null
	ret void
}


Add a test case for r208252. Prior to r208252, the FMA 231 family was marked as isCommutable. However the memory variants of this family are not commutable. Therefore, we did not implemented the findCommutedOpIndices for those variants and missed that the default implementation (more or less: commute indices 1 and 2) was firing behind our back. As a result, as demonstrated in the test case before the fix, we were transforming a = b * c + a into a = a * c + b.

; RUN: llc -fp-contract=fast -mattr=+fma -disable-cgp < %s -o - | FileCheck %s
; Check that the 2nd and 3rd arguments of fmaXXX231 reg1, reg2, mem3 are not commuted.
; <rdar://problem/16800495>
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx"

; CHECK-LABEL: test1:
; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
; CHECK-NOT {{.*}}, %xmm0
; %addr lives in rdi.
; %addr2 lives in rsi.
; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]]
; The assembly syntax is in the reverse order.
; CHECK: vfmadd231ss (%rdi), [[ADDR2]], %xmm0
define void @test1(float* %addr, float* %addr2, float %arg) {
entry:
  br label %loop

loop:
  %sum0 = phi float [ %fma, %loop ], [ %arg, %entry ]
  %addrVal = load float* %addr, align 4
  %addr2Val = load float* %addr2, align 4
  %fmul = fmul float %addrVal, %addr2Val
  %fma = fadd float %sum0, %fmul
  br i1 true, label %exit, label %loop

exit:
  store float %fma, float* %addr, align 4
  ret void
}